Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9A41C433FE for ; Fri, 3 Dec 2021 16:32:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381910AbhLCQfi (ORCPT ); Fri, 3 Dec 2021 11:35:38 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:47306 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245728AbhLCQfh (ORCPT ); Fri, 3 Dec 2021 11:35:37 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8895062C1F; Fri, 3 Dec 2021 16:32:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5CFAC53FCD; Fri, 3 Dec 2021 16:32:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1638549132; bh=GJjzs4CbpbnwXQCUCUM4r55kJfSeTbIx8bPqA88zfio=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=cUIjF0jpDhTzM/R2sl3sUQj18NhOt/pioC+isxM6j8INylDBds1F/iPH1v4favTqT MywEB3cgC9Q6fwnS1w2TBnoWH0SY8An9U25nzj5EGjOgr9cj7oUYcoSdmUL/DEBru9 L2RiloOfE8XlvYr/yiYdX5ALpNS8jVrQJjwx8TaHqUZw//UhKjWearLtX/Kx9mQVCK z5e8Ss9m5jQD3HIRCmlBBeVNIC83xGXts/UGENorL5an0gzx5bCOEyzgFyAooJjh6C 3qZMhlCj7GcUxv8lNES8uAaoNlE7U1bwzd0KguxNn094uEoNezHAUMhpB21kKP+Gwn zc0ZUjACqnCPQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mtBTm-009e3e-Uk; Fri, 03 Dec 2021 16:32:11 +0000 Date: Fri, 03 Dec 2021 16:32:10 +0000 Message-ID: <87zgphlkdx.wl-maz@kernel.org> From: Marc Zyngier To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: Re: [PATCH v2 3/8] irqchip/apple-aic: Add cpumasks for E and P cores In-Reply-To: References: <20211201134909.390490-1-maz@kernel.org> <20211201134909.390490-4-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 01 Dec 2021 16:08:13 +0000, Mark Rutland wrote: > > On Wed, Dec 01, 2021 at 01:49:04PM +0000, Marc Zyngier wrote: > > In order to be able to tell the core IRQ code about the affinity > > of the PMU interrupt in later patches, compute the cpumasks of the > > P and E cores at boot time. > > > > This relies on the affinity scheme used by the vendor, which seems > > to work for the couple of SoCs that are out in the wild. > > ... but may change at any arbitrary point in future? Crystal balls are in short supply, sorry! ;-) > Can we please put the affinity in the DT, like we do for other SoCs and > devices? > > I don't think we should treat this HW specially in this regard; we certaintly > don't want other folk hard-coding system topology in their irqchip driver, and > it should be possible to do something like the ppi-partitions binding, no? The PPI partition is totally overkill here. What it deals with is multiple devices sharing a single PPI across the system. Here, we can invent our own interrupt number, so the sharing is avoided by construction (the joy of not having an interrupt controller the first place!). I'm happy to stick the affinity in the DT (after all, it is likely that other devices on these systems have the same requirements) and have it consumed by the irqchip driver. I only need to find a way that doesn't completely invalidate the existing binding... M. -- Without deviation from the norm, progress is not possible.