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b=Nv+7KQwmy4wTs96w46RZbWqtA8HbvFZlv9l9BXjkd6oLXVcGknUM6GTEO+OVc1O017wKqIKETDww6MTFsnE2Lc3CU9yv6XX+szwZ/QhI3wIFPKj7rSfvVcjIKlWnEuaDwB0nHrI39N/rwSS5OO1e46fuC79UGXHB74JiwW6FbBI= Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by DU2PR04MB9050.eurprd04.prod.outlook.com (2603:10a6:10:2e5::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4755.14; Sun, 5 Dec 2021 12:53:51 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::82e:6ad2:dd1d:df43]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::82e:6ad2:dd1d:df43%8]) with mapi id 15.20.4713.027; Sun, 5 Dec 2021 12:53:51 +0000 From: Peng Fan To: Daniel Lezcano , "Peng Fan (OSS)" , "tglx@linutronix.de" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" CC: "kernel@pengutronix.de" , "festevam@gmail.com" , dl-linux-imx , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "van.freenix@gmail.com" Subject: RE: [PATCH 2/2] clocksource: timer-imx-sysctr: set cpumask to cpu_possible_mask Thread-Topic: [PATCH 2/2] clocksource: timer-imx-sysctr: set cpumask to cpu_possible_mask Thread-Index: AQHX5rIpXvvERj8j10espZggT53Quawe/42AgATgKoA= Date: Sun, 5 Dec 2021 12:53:51 +0000 Message-ID: References: <20211201125030.2307746-1-peng.fan@oss.nxp.com> <20211201125030.2307746-2-peng.fan@oss.nxp.com> <80578aa9-35dd-02ca-fb07-5895991572e2@linaro.org> In-Reply-To: <80578aa9-35dd-02ca-fb07-5895991572e2@linaro.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; 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charset="koi8-r" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ab90afc9-ab76-466d-70fc-08d9b7ee4980 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Dec 2021 12:53:51.1426 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: FZHczrv5zU9A0vkx4Dyef94hzWaKx6G1/H1gAWXX/rMy7ZrY9SyrVJ5N7HIpQmzMVF3MgpOHeJtBolPLl3r6Zw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9050 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Subject: Re: [PATCH 2/2] clocksource: timer-imx-sysctr: set cpumask to > cpu_possible_mask >=20 > On 01/12/2021 13:50, Peng Fan (OSS) wrote: > > From: Peng Fan > > > > Actually we have CLOCK_EVT_FEAT_DYNIRQ, the irq affinity will be > > runtime changed and no issue. But the system counter timer is not tied > > to CPU0, so use cpu_possible_mask here. >=20 > Did you mean: >=20 > "There is no reason to tie the system counter timer to CPU0, change its > affinity to cpu_possible_mask. >=20 > Moreover, the timer has the flag CLOCK_EVT_FEAT_DYNIRQ set, changing to > cpu_possibl_mask will reduce the number of wakeups related to the system > timer" The syctr interrupt could be set affinity to any cores in the SoC. Default = affinity is set to cpu 0. This timer will be used as broadcast timer on all the i.MX SoCs. Because DY= NIRQ flag set, the core time framework will runtime set the interrupt affinity t= o the cores that needs to wake up and the cpumask will runtime set to the core that wil= l be wake up. So even the sysctr initialization use cpumask 0, there is no issue= , the current patch is just use cpu_possible_mask to show the fact that the timer supports routed to all the cpu cores and nothing else. Thanks, Peng. >=20 > ? >=20 > Note you may want to explain why 'there is no reason' >=20 >=20 > > Signed-off-by: Peng Fan > > --- > > drivers/clocksource/timer-imx-sysctr.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/clocksource/timer-imx-sysctr.c > > b/drivers/clocksource/timer-imx-sysctr.c > > index 2b309af11266..55a8e198d2a1 100644 > > --- a/drivers/clocksource/timer-imx-sysctr.c > > +++ b/drivers/clocksource/timer-imx-sysctr.c > > @@ -119,7 +119,7 @@ static struct timer_of to_sysctr =3D { > > > > static void __init sysctr_clockevent_init(void) { > > - to_sysctr.clkevt.cpumask =3D cpumask_of(0); > > + to_sysctr.clkevt.cpumask =3D cpu_possible_mask; > > > > clockevents_config_and_register(&to_sysctr.clkevt, > > timer_of_rate(&to_sysctr), > > >=20 >=20 > -- > inaro.org%2F&data=3D04%7C01%7Cpeng.fan%40nxp.com%7C1fec86efbd5 > 4498106c508d9b57d9e2a%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0% > 7C0%7C637740373391832133%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC > 4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000& > amp;sdata=3Dq98PLDpC8h7jt%2BjvCeXZAf2F5ZzJsMMS613OSHmjDr0%3D&am > p;reserved=3D0> Linaro.org =81 Open source software for ARM SoCs >=20 > Follow Linaro: > acebook.com%2Fpages%2FLinaro&data=3D04%7C01%7Cpeng.fan%40nxp. > com%7C1fec86efbd54498106c508d9b57d9e2a%7C686ea1d3bc2b4c6fa92cd > 99c5c301635%7C0%7C0%7C637740373391832133%7CUnknown%7CTWFpb > GZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI > 6Mn0%3D%7C3000&sdata=3DKmuInvkOIYTEcR4sFHhEbQSJczarvwwm8slI > GfjCa70%3D&reserved=3D0> Facebook | > .com%2F%23!%2Flinaroorg&data=3D04%7C01%7Cpeng.fan%40nxp.com% > 7C1fec86efbd54498106c508d9b57d9e2a%7C686ea1d3bc2b4c6fa92cd99c5c > 301635%7C0%7C0%7C637740373391832133%7CUnknown%7CTWFpbGZsb3 > d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0 > %3D%7C3000&sdata=3DmS9fXmEPB1798JRJWfhEpXcbdWfRiSb5%2FH6cz7 > 9rl8E%3D&reserved=3D0> Twitter | > inaro.org%2Flinaro-blog%2F&data=3D04%7C01%7Cpeng.fan%40nxp.com% > 7C1fec86efbd54498106c508d9b57d9e2a%7C686ea1d3bc2b4c6fa92cd99c5c > 301635%7C0%7C0%7C637740373391832133%7CUnknown%7CTWFpbGZsb3 > d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0 > %3D%7C3000&sdata=3D%2BlsiYye7ZBW8jClBsZbSHkcbD0hqvvvx0H9SAlUV > e7U%3D&reserved=3D0> Blog