From:   Vignesh Raghavendra <vigneshr@ti.com>
To:     Rob Herring <robh+dt@kernel.org>, Tero Kristo <kristo@kernel.org>,
        Nishanth Menon <nm@ti.com>
CC:     Vignesh Raghavendra <vigneshr@ti.com>,
        <linux-omap@vger.kernel.org>, Peng Fan <peng.fan@nxp.com>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets
Date:   Mon, 6 Dec 2021 18:40:18 +0530
Message-ID: <163879570036.16658.17037182694525892897.b4-ty@ti.com>
In-Reply-To: <20211113043638.4358-1-nm@ti.com>
References: <20211113043638.4358-1-nm@ti.com>
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Hi Nishanth Menon,
 
On Fri, 12 Nov 2021 22:36:38 -0600, Nishanth Menon wrote:
> A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of
> 64 bytes and 16-way set-associative cache structure.
> 

Replaced A53 referenc with A72 locally and applied.

> 1MB of L2 / 64 (line length) = 16384 ways
> 16384 ways / 16 = 1024 sets
> 
> Fix the l2 cache-sets.
> 
> [...]
 
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
 
[1/1] arm64: dts: ti: k3-j7200: Fix the L2 cache sets
      commit: d0c826106f3fc11ff97285102b576b65576654ae
 
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
 
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
 
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
 
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to this mail.
 
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh