Date:   Mon, 6 Dec 2021 11:48:02 -0500
From:   =?utf-8?B?TsOtY29sYXMgRi4gUi4gQS4=?= Prado 
        <nfraprado@collabora.com>
To:     Chun-Jie Chen <chun-jie.chen@mediatek.com>
Cc:     Matthias Brugger <matthias.bgg@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Nicolas Boichat <drinkcat@chromium.org>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
        srv_heupstream@mediatek.com,
        Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [v1 4/5] arm64: dts: mediatek: Correct Nor Flash clock of MT8192
Message-ID: <20211206164802.33ygybxt2bi2wom6@notapiano>
References: <20210825011120.30481-1-chun-jie.chen@mediatek.com>
 <20210825011120.30481-5-chun-jie.chen@mediatek.com>
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In-Reply-To: <20210825011120.30481-5-chun-jie.chen@mediatek.com>
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Hi,

On Wed, Aug 25, 2021 at 09:11:19AM +0800, Chun-Jie Chen wrote:
> update nor flash clock to the real one.

Same comment from patch 1.

Reviewed-by: N?colas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
N?colas

> 
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index d1c85d3e152b..db6f4c6dc404 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -464,9 +464,9 @@
>  			compatible = "mediatek,mt8192-nor";
>  			reg = <0 0x11234000 0 0xe0>;
>  			interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>,
> -				 <&clk26m>,
> -				 <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
> +				 <&infracfg CLK_INFRA_FLASHIF_SFLASH>,
> +				 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
>  			clock-names = "spi", "sf", "axi";
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> -- 
> 2.18.0
> 
>