Date:   Mon, 6 Dec 2021 15:25:19 -0600
From:   Patrick Williams <patrick@stwcx.xyz>
To:     Howard Chiu <howard10703049@gmail.com>
Cc:     arnd@arndb.de, olof@lixom.net, soc@kernel.org, robh+dt@kernel.org,
        joel@jms.id.au, andrew@aj.id.au,
        linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org,
        Howard Chiu <howard.chiu@quantatw.com>
Subject: Re: [PATCH v6] ARM: dts: aspeed: Adding Facebook Bletchley BMC
Message-ID: <Ya5/v+VhOM9o9BtQ@heinlein>
References: <20211201033738.121846-1-howard.chiu@quantatw.com>
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On Wed, Dec 01, 2021 at 11:37:38AM +0800, Howard Chiu wrote:
> Initial introduction of Facebook Bletchley equipped with
> Aspeed 2600 BMC SoC.
>=20
> Signed-off-by: Howard Chiu <howard.chiu@quantatw.com>
>=20

=2E..

> Change since v2:
> - Remove uart5 workaround
> - Remove gpio nodes of pca9552/pca9539
> - Modify gpio-line-name of led/power/presence pins with openbmc pattern

A number of the GPIOs do not have defined openbmc patterns for them yet.  T=
he
names you have chosen are ok for now, but we will be changing them as we re=
fine
development of this machine further.

> +		gpio-line-names =3D
> +		"SLED0_MS_DETECT1","SLED0_VBUS_BMC_EN","SLED0_INA230_ALERT","SLED0_P12=
V_STBY_ALERT",
> +		"SLED0_SSD_ALERT","SLED0_MS_DETECT0","SLED0_RST_CCG5","SLED0_FUSB302_I=
NT",
> +		"SLED0_MD_STBY_RESET","SLED0_MD_IOEXP_EN_FAULT","SLED0_MD_DIR","SLED0_=
MD_DECAY",
> +		"SLED0_MD_MODE1","SLED0_MD_MODE2","SLED0_MD_MODE3","power-host0";

Such as these...

> --=20
> 2.25.1
>=20

Otherwise,

Reviewed-by: Patrick Williams <patrick@stwcx.xyz>

--=20
Patrick Williams

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