Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB230C433EF for ; Tue, 7 Dec 2021 06:06:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236514AbhLGGJd (ORCPT ); Tue, 7 Dec 2021 01:09:33 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:37050 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230094AbhLGGJc (ORCPT ); Tue, 7 Dec 2021 01:09:32 -0500 X-UUID: c7009bf4b7c64fe49c59bec8c178623c-20211207 X-UUID: c7009bf4b7c64fe49c59bec8c178623c-20211207 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 628431408; Tue, 07 Dec 2021 14:05:58 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 7 Dec 2021 14:05:56 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 7 Dec 2021 14:05:56 +0800 From: qizhong cheng To: Ryder Lee , Lorenzo Pieralisi , Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Jianjun Wang CC: , , , , , Subject: [PATCH] PCI: mediatek: Delay 100ms to wait power and clock to become stable Date: Tue, 7 Dec 2021 14:05:50 +0800 Message-ID: <20211207060550.20918-1-qizhong.cheng@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Signed-off-by: qizhong cheng Change-Id: Ia9abe1e763564a5bad1d045fd268c38e76e2ae95 --- drivers/pci/controller/pcie-mediatek.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 2f3f974977a3..a61ea3940471 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) */ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + /* + * Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should + * be delayed 100ms (TPVPERL) for the power and clock to become stable. + */ + msleep(100); + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ val = readl(port->base + PCIE_RST_CTRL); val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | -- 2.25.1