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[83.54.181.27]) by smtp.gmail.com with ESMTPSA id z6sm13958561wrm.93.2021.12.07.02.49.28 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Dec 2021 02:49:29 -0800 (PST) From: Sergio Paracuellos To: linux-pci@vger.kernel.org Cc: tsbogend@alpha.franken.de, lorenzo.pieralisi@arm.com, bhelgaas@google.com, linux@roeck-us.net, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/5] MIPS: ralink: implement 'pcibios_root_bridge_prepare()' Date: Tue, 7 Dec 2021 11:49:21 +0100 Message-Id: <20211207104924.21327-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211207104924.21327-1-sergio.paracuellos@gmail.com> References: <20211207104924.21327-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCI core code call 'pcibios_root_bridge_prepare()' function inside function 'pci_register_host_bridge()'. This point is very good way to properly enter into this MIPS ralink specific code to properly setup I/O coherency units with PCI memory addresses. Signed-off-by: Sergio Paracuellos --- arch/mips/ralink/mt7621.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index bd71f5b14238..d6efffd4dd20 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #include #include @@ -22,6 +24,35 @@ static void *detect_magic __initdata = detect_memory_region; +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) +{ + struct resource_entry *entry; + resource_size_t mask; + + entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); + if (!entry) { + pr_err("Cannot get memory resource\n"); + return -EINVAL; + } + + if (mips_cps_numiocu(0)) { + /* + * Hardware doesn't accept mask values with 1s after + * 0s (e.g. 0xffef), so warn if that's happen + */ + mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK; + WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask); + + write_gcr_reg1_base(entry->res->start); + write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); + pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n", + (unsigned long long)read_gcr_reg1_base(), + (unsigned long long)read_gcr_reg1_mask()); + } + + return 0; +} + phys_addr_t mips_cpc_default_phys_base(void) { panic("Cannot detect cpc address"); -- 2.33.0