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[94.29.46.111]) by smtp.googlemail.com with ESMTPSA id s15sm1663658lfp.252.2021.12.07.04.05.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Dec 2021 04:05:43 -0800 (PST) Subject: Re: [PATCH 1/3] ALSA: hda/tegra: Skip reset on BPMP devices To: Sameer Pujar , tiwai@suse.com, broonie@kernel.org, lgirdwood@gmail.com, robh+dt@kernel.org, thierry.reding@gmail.com, perex@perex.cz Cc: jonathanh@nvidia.com, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Mohan Kumar References: <1638858770-22594-1-git-send-email-spujar@nvidia.com> <1638858770-22594-2-git-send-email-spujar@nvidia.com> <7742adae-cdbe-a9ea-2cef-f63363298d73@gmail.com> <8fd704d9-43ce-e34a-a3c0-b48381ef0cd8@nvidia.com> From: Dmitry Osipenko Message-ID: <56bb43b6-8d72-b1de-4402-a2cb31707bd9@gmail.com> Date: Tue, 7 Dec 2021 15:05:42 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <8fd704d9-43ce-e34a-a3c0-b48381ef0cd8@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 07.12.2021 15:00, Sameer Pujar пишет: > > > On 12/7/2021 3:52 PM, Dmitry Osipenko wrote: >> 07.12.2021 09:32, Sameer Pujar пишет: >>> HDA regression is recently reported on Tegra194 based platforms. >>> This happens because "hda2codec_2x" reset does not really exist >>> in Tegra194 and it causes probe failure. All the HDA based audio >>> tests fail at the moment. This underlying issue is exposed by >>> commit c045ceb5a145 ("reset: tegra-bpmp: Handle errors in BPMP >>> response") which now checks return code of BPMP command response. >>> >>> The failure can be fixed by avoiding above reset in the driver, >>> but the explicit reset is not necessary for Tegra devices which >>> depend on BPMP. On such devices, BPMP ensures reset application >>> during unpowergate calls. Hence skip reset on these devices >>> which is applicable for Tegra186 and later. >> The power domain is shared with the display, AFAICS. The point of reset >> is to bring h/w into predictable state. It doesn't make sense to me to >> skip the reset. > > Yes the power-domain is shared with display. As mentioned above, > explicit reset in driver is not really necessary since BPMP is already > doing it during unpowergate stage. So the h/w is already ensured to be > in a good state. If you'll reload the driver module, then h/w won't be reset.