Subject: Re: [PATCH 1/3] ALSA: hda/tegra: Skip reset on BPMP devices
To:     Sameer Pujar <spujar@nvidia.com>, tiwai@suse.com,
        broonie@kernel.org, lgirdwood@gmail.com, robh+dt@kernel.org,
        thierry.reding@gmail.com, perex@perex.cz
Cc:     jonathanh@nvidia.com, alsa-devel@alsa-project.org,
        devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org, stable@vger.kernel.org,
        Mohan Kumar <mkumard@nvidia.com>
References: <1638858770-22594-1-git-send-email-spujar@nvidia.com>
 <1638858770-22594-2-git-send-email-spujar@nvidia.com>
 <7742adae-cdbe-a9ea-2cef-f63363298d73@gmail.com>
 <8fd704d9-43ce-e34a-a3c0-b48381ef0cd8@nvidia.com>
 <56bb43b6-8d72-b1de-4402-a2cb31707bd9@gmail.com>
 <4855e9c4-e4c2-528b-c9ad-2be7209dc62a@nvidia.com>
From:   Dmitry Osipenko <digetx@gmail.com>
Message-ID: <5d441571-c1c2-5433-729f-86d6396c2853@gmail.com>
Date:   Tue, 7 Dec 2021 17:07:26 +0300
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101
 Thunderbird/78.14.0
MIME-Version: 1.0
In-Reply-To: <4855e9c4-e4c2-528b-c9ad-2be7209dc62a@nvidia.com>
Content-Type: text/plain; charset=utf-8
Content-Language: en-US
Content-Transfer-Encoding: 8bit
Precedence: bulk

07.12.2021 15:40, Sameer Pujar пишет:
> 
> 
> On 12/7/2021 5:35 PM, Dmitry Osipenko wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> 07.12.2021 15:00, Sameer Pujar пишет:
>>>
>>> On 12/7/2021 3:52 PM, Dmitry Osipenko wrote:
>>>> 07.12.2021 09:32, Sameer Pujar пишет:
>>>>> HDA regression is recently reported on Tegra194 based platforms.
>>>>> This happens because "hda2codec_2x" reset does not really exist
>>>>> in Tegra194 and it causes probe failure. All the HDA based audio
>>>>> tests fail at the moment. This underlying issue is exposed by
>>>>> commit c045ceb5a145 ("reset: tegra-bpmp: Handle errors in BPMP
>>>>> response") which now checks return code of BPMP command response.
>>>>>
>>>>> The failure can be fixed by avoiding above reset in the driver,
>>>>> but the explicit reset is not necessary for Tegra devices which
>>>>> depend on BPMP. On such devices, BPMP ensures reset application
>>>>> during unpowergate calls. Hence skip reset on these devices
>>>>> which is applicable for Tegra186 and later.
>>>> The power domain is shared with the display, AFAICS. The point of reset
>>>> is to bring h/w into predictable state. It doesn't make sense to me to
>>>> skip the reset.
>>> Yes the power-domain is shared with display. As mentioned above,
>>> explicit reset in driver is not really necessary since BPMP is already
>>> doing it during unpowergate stage. So the h/w is already ensured to be
>>> in a good state.
>> If you'll reload the driver module, then h/w won't be reset.
> 
> How the reload case would be different? Can you please specify more
> details if you are referring to a particular scenario?

You have a shared power domain. Since power domain can be turned off
only when nobody keeps domain turned on, you now making reset of HDA
controller dependent on the state of display driver. Do you want to have
inconsistent h/w reset behaviour depending on the runtime state of
display driver?