Message-ID: <b7f5a30c-4148-32d8-39b2-2ba8bb64635a@canonical.com>
Date:   Wed, 8 Dec 2021 09:50:22 +0100
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Subject: Re: [PATCH v4 5/7] clk: samsung: clk-pll: Add support for pll1417x
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To:     Sam Protsenko <semen.protsenko@linaro.org>,
        David Virag <virag.david003@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Sylwester Nawrocki <s.nawrocki@samsung.com>,
        Tomasz Figa <tomasz.figa@gmail.com>,
        Chanwoo Choi <cw00.choi@samsung.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        linux-arm-kernel@lists.infradead.org,
        linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
References: <20211206153124.427102-1-virag.david003@gmail.com>
 <20211206153124.427102-6-virag.david003@gmail.com>
 <CAPLW+4kSDHUsvHo0njykTTRGqaAehRt6MXdJF73OzR47avOm9Q@mail.gmail.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
In-Reply-To: <CAPLW+4kSDHUsvHo0njykTTRGqaAehRt6MXdJF73OzR47avOm9Q@mail.gmail.com>
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On 07/12/2021 20:00, Sam Protsenko wrote:
> On Mon, 6 Dec 2021 at 17:32, David Virag <virag.david003@gmail.com> wrote:
>>
>> pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
>> It is similar enough to pll0822x that practically the same code can
>> handle both. The difference that's to be noted is that when defining a
>> pl1417x PLL, the "con" parameter of the PLL macro should be set to the
>> CON1 register instead of CON3, like this:
>>
>>     PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
>>         PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
>>         NULL),
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>> Signed-off-by: David Virag <virag.david003@gmail.com>
>> ---
>> Changes in v2:
>>   - Nothing
>>
>> Changes in v3:
>>   - Nothing
>>
>> Changes in v4:
>>   - Added R-b tag by Krzysztof Kozlowski
>>
>>  drivers/clk/samsung/clk-pll.c | 1 +
>>  drivers/clk/samsung/clk-pll.h | 1 +
>>  2 files changed, 2 insertions(+)
>>
>> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
>> index 83d1b03647db..70cdc87f714e 100644
>> --- a/drivers/clk/samsung/clk-pll.c
>> +++ b/drivers/clk/samsung/clk-pll.c
>> @@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>>                 else
>>                         init.ops = &samsung_pll35xx_clk_ops;
>>                 break;
>> +       case pll_1417x:
> 
> I wonder why this switch have a bunch of fall through cases, but none
> marked with "fallthrough;" line, and both checkpatch and "make" turn
> blind eye on that? Anyway, I guess it's ok as is, just an observation.
> 

I think the fallthrough is needed for non-obvious cases where one case
has some code and misses a break. Something like:

switch () {
case a:
case b:
case c:
    foobar();
}

is obvious/explicit and does not need fallthrough.

Best regards,
Krzysztof