Message-ID: <0ca44f61-f7f1-0440-e1e1-8d5e8aa9b540@gmail.com>
Date:   Thu, 9 Dec 2021 16:28:37 +0800
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To:     Jim Mattson <jmattson@google.com>, Andi Kleen <ak@linux.intel.com>,
        Kim Phillips <kim.phillips@amd.com>
Cc:     Paolo Bonzini <pbonzini@redhat.com>,
        Sean Christopherson <seanjc@google.com>,
        Vitaly Kuznetsov <vkuznets@redhat.com>,
        Wanpeng Li <wanpengli@tencent.com>,
        Joerg Roedel <joro@8bytes.org>, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org, Like Xu <likexu@tencent.com>
References: <20211130074221.93635-1-likexu@tencent.com>
 <20211130074221.93635-5-likexu@tencent.com>
 <CALMp9eRAxBFE5mYw=isUSsMTWZS2VOjqZfgh0r3hFuF+5npCAQ@mail.gmail.com>
From:   Like Xu <like.xu.linux@gmail.com>
Organization: Tencent
Subject: Re: [PATCH v2 4/6] KVM: x86/pmu: Add pmc->intr to refactor
 kvm_perf_overflow{_intr}()
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On 9/12/2021 12:25 pm, Jim Mattson wrote:
> 
> Not your change, but if the event is counting anything based on
> cycles, and the guest TSC is scaled to run at a different rate from
> the host TSC, doesn't the initial value of the underlying hardware
> counter have to be adjusted as well, so that the interrupt arrives
> when the guest's counter overflows rather than when the host's counter
> overflows?

I've thought about this issue too and at least the Intel Specification
did not let me down on this detail:

	"The counter changes in the VMX non-root mode will follow
	VMM's use of the TSC offset or TSC scaling VMX controls"

Not knowing if AMD or the real world hardware
will live up to this expectation and I'm pessimistic.

cc Andi and Kim.