From:   Zev Weiss <zweiss@equinix.com>
To:     =?iso-8859-1?Q?Jonathan_Neusch=E4fer?= <j.neuschaefer@gmx.net>
CC:     Andy Shevchenko <andy.shevchenko@gmail.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        Tomer Maimon <tmaimon77@gmail.com>,
        "openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Linus Walleij <linus.walleij@linaro.org>
Subject: Re: [PATCH v2 5/8] pinctrl: nuvoton: Add driver for WPCM450
Thread-Topic: [PATCH v2 5/8] pinctrl: nuvoton: Add driver for WPCM450
Thread-Index: AQHX7NZz4X2KiWn6NUSUMKT7zlTdMg==
Date:   Thu, 9 Dec 2021 08:26:24 +0000
Message-ID: <20211209082623.GF25091@packtop>
References: <20211207210823.1975632-1-j.neuschaefer@gmx.net>
 <20211207210823.1975632-6-j.neuschaefer@gmx.net>
 <CAHp75Vew=M_ofNM5pmeHtTJHXRUbbO4RrtgYAtLBznTBm3CS6Q@mail.gmail.com>
 <YbC6Bv2teZ5CFhFQ@latitude>
In-Reply-To: <YbC6Bv2teZ5CFhFQ@latitude>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?Q?csTLhhqKPdJ6OPUhgbwD78Daf0LcNYnv5M1pGfXD4RVeIWKTnfu7o2nrxq?=
 =?iso-8859-1?Q?R4OlNNz4y+cwb0GQEOPXbP0m8wau8QHwo27BOXkWnikpn06c4788gC2kk7?=
 =?iso-8859-1?Q?AZcDi0Gi9Z5U6lEdDIHo00aYCa8FpCQ0Sjv74u9uypUKEdDYpUGbpnBqxS?=
 =?iso-8859-1?Q?ohjlZzXeITdIQltrTnIRU3Pthaq6SxYw3ChQEkyxkXVz+7FgXaXj+5zBSV?=
 =?iso-8859-1?Q?P1dTSSIXha/rJZ1vBb1W2tfb9pZNVkHn2PMZR0kLIddqEAkR5p1AMvY9dR?=
 =?iso-8859-1?Q?SY+9wROmK37Q95h3VZe68PJx7r8ADPDEGR42OUwQPP4Xc57Slh8+qS/R9I?=
 =?iso-8859-1?Q?Mg+K26StqTC/W5e0CdgjETda9mDl+Ymfxh77yq+nrzRt/rCNtZGsDNWqiH?=
 =?iso-8859-1?Q?8Ny+RoIeiGpAm9JbZndU/OrOOcBNZSaxmIQlolxGRH+djuh2JavpsZxmkM?=
 =?iso-8859-1?Q?RFUvNsQKtDwcuGSrb1jVYd9Y9fNhq4b4fJji52zCHi/JO5VQCYprqNuIT3?=
 =?iso-8859-1?Q?+TyWw8+FKGYZYQyaFVRxkJdEp2oJw0l0CttHMnh02PCO1ZXz/glx4/r66b?=
 =?iso-8859-1?Q?kSWlEibUkZJr1TzQuSCn8RXXHBTwDpetFJ2fYeLY6FGJri1ejiTzC4Sk7C?=
 =?iso-8859-1?Q?fiJasL2LOPh4b5TSosXmDQ1rlMwC/3BlXCrr7xHGN7TI73YGnqBz9qcEG6?=
 =?iso-8859-1?Q?cbhYVZEtaQZ/5ORdxWk7Ok+WL4h7Y9JfysfbC9WK2yGT0/FGuWrbvI0cWX?=
 =?iso-8859-1?Q?+8ezkMO6pd87qgnD2MFuz2WcTAuRR6mt1an+PprzDa10i1ixF4zR/juDMe?=
 =?iso-8859-1?Q?3kt41j3O6zSlbzSzfhx3W3Qhu/mJfXR6zSYG+qQbRqDB5fKquJswJDZF8y?=
 =?iso-8859-1?Q?E0Kp0VsyihHo4EW2cAOEMB2OV8gTxdOXziScrryOV4bCXCfLq6wjkO5/HX?=
 =?iso-8859-1?Q?8F6o9+0sxSfGu3TYrMQDoChLE1+74Qznet88OAf7JLmOJ77m62+7tUoKrf?=
 =?iso-8859-1?Q?+bfNaDadNwpQSZqvGvhloJmD1jkzRW/eU7yh3rvViyvp6YGM4CUGC7nwSm?=
 =?iso-8859-1?Q?jfuwOq28+V08ckd99D5qid6ouKAkJOP4nehhqb8tUDYM7kOSgsQsl6WHPG?=
 =?iso-8859-1?Q?jzYwCQlLyl13TAWZbpVjksXcM/oR/1PzEC9i6043DKbunVslv3YTFCAqNq?=
 =?iso-8859-1?Q?8c+7PP/vJqt1Q5FTy3g6QdEFx8EgOM1u1KhxZrvLa3lzwuv1TEg55cgFcs?=
 =?iso-8859-1?Q?nOkwaSYy2l816IB7kZIBX/b8RKIENscn23OtzKkTFyOaDTR4WwcI1yE2PT?=
 =?iso-8859-1?Q?pODXnCvQjsqIN/V7i36JvYAJ2XoNm2NGd9zaz8YvGTulJIi4oJl1UQjKvE?=
 =?iso-8859-1?Q?ZwbOH7cDFXa95njFBZjYrebRxdjyVyjBQVtGn34NXO5n65sHmc6zFNqUCR?=
 =?iso-8859-1?Q?sa2E9tHv2T7TZT6S2X91+YflNrEp08ALgOQUiUpZx0r1gdOeKoQVvX264A?=
 =?iso-8859-1?Q?CszC7kG0ko5sPGMmYT5g3pVXE9dEYQc3vctGLRmmzRWExOav5ujzt6FAbW?=
 =?iso-8859-1?Q?vSg8U9cr7L0lLn1kWzlANEAidha0Eg0x6C+GrPuGUlEnaPh2TQThAc5Lzw?=
 =?iso-8859-1?Q?tDcA2rkxmigLnqX+xqaDG8A5gNUOocD7LAacRBajZBrn8mFKqw9jpNs5oj?=
 =?iso-8859-1?Q?9q7AOADJOBKHkvgJj9c=3D?=
Content-Type: text/plain; charset="iso-8859-1"
Content-ID: <5E60DF1721D9D245A7F75B8F76B0AAE8@namprd04.prod.outlook.com>
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: equinix.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: DM8PR04MB8007.namprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 1e1e5df5-9eaf-4fea-8b43-08d9baed9660
X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Dec 2021 08:26:24.0918
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 72adb271-2fc7-4afe-a5ee-9de6a59f6bfb
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: HVg0eiAqopFJNIJzbLs34QuOyg/EcF00Z/Xo1IgBC4a3hEUD6asL72ybANw9BbuSKiPfKx5SRt2bGQ2jrISkmA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR04MB7944
X-Proofpoint-GUID: GSu-yJY626MFc2Vj6OqkrD57I2stm8zy
X-Proofpoint-ORIG-GUID: GSu-yJY626MFc2Vj6OqkrD57I2stm8zy
X-Proofpoint-Virus-Version: vendor=baseguard
 engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513
 definitions=2021-12-09_03,2021-12-08_01,2021-12-02_01
X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0
 mlxscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1011
 phishscore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501
 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1
 engine=8.12.0-2110150000 definitions=main-2112090044
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Wed, Dec 08, 2021 at 05:58:30AM PST, Jonathan Neusch=E4fer wrote:
>Hi,
>
>On Wed, Dec 08, 2021 at 01:24:18PM +0200, Andy Shevchenko wrote:
>> On Tuesday, December 7, 2021, Jonathan Neusch=E4fer <j.neuschaefer@gmx.n=
et>
>
><snip>
>
>> > +static void wpcm450_gpio_irqhandler(struct irq_desc *desc)
>> > +{
>> > +       struct wpcm450_gpio *gpio =3D gpiochip_get_data(irq_desc_
>> > get_handler_data(desc));
>> > +       struct wpcm450_pinctrl *pctrl =3D gpio->pctrl;
>> > +       struct irq_chip *chip =3D irq_desc_get_chip(desc);
>> > +       unsigned long pending;
>> > +       unsigned long flags;
>> > +       unsigned long ours;
>> > +       unsigned int bit;
>> > +
>> > +       ours =3D ((1UL << gpio->num_irqs) - 1) << gpio->first_irq_bit;
>>
>>
>> BIT()
>
>I'll use it, but in this case, I think it doesn't simplify much the
>whole expression all that much. Is there perhaps a macro that
>constructs a continuous bitmask of N bits, perhaps additionally
>left-shifted by M bits?
>
>Maybe somewhere in the bitmap_* API...
>

There's GENMASK(), though it takes a high bit and low bit rather than a
bit position and count, so it'd require a small bit of arithmetic, e.g.

  lastbit =3D gpio->first_irq_bit + gpio->num_irqs - 1;
  ours =3D GENMASK(lastbit, gpio->first_irq_bit);

or a manual shift:

  ours =3D GENMASK(gpio->num_irqs - 1, 0) << gpio->first_irq_bit;

(I don't have any terribly strong opinions on which of these is best,
personally.)


Zev