Date:   Thu, 9 Dec 2021 17:20:02 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Milind Parab <mparab@cadence.com>
Cc:     Swapnil Kashinath Jakhade <sjakhade@cadence.com>,
        "kishon@ti.com" <kishon@ti.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
        "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "a-govindraju@ti.com" <a-govindraju@ti.com>
Subject: Re: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
 multilink configuration
Message-ID: <YbHtanITI9I/cONn@matsya>
References: <20211022170236.18839-1-sjakhade@cadence.com>
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On 09-12-21, 06:11, Milind Parab wrote:
> Hi Vinod,
> 
> Do you have any further comments on this.
> The implementation follows the same approach as is done for Cadence Torrent multiprotocol Phy

Pls do *not* top post!

Sure i will look into it soon..

> 
> Regards,
> Milind
> 
> >-----Original Message-----
> >From: Swapnil Kashinath Jakhade <sjakhade@cadence.com>
> >Sent: Thursday, December 2, 2021 7:43 PM
> >To: Vinod Koul <vkoul@kernel.org>
> >Cc: kishon@ti.com; robh+dt@kernel.org; p.zabel@pengutronix.de; linux-
> >phy@lists.infradead.org; linux-kernel@vger.kernel.org;
> >devicetree@vger.kernel.org; Milind Parab <mparab@cadence.com>; a-
> >govindraju@ti.com
> >Subject: RE: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
> >multilink configuration
> >
> >Hi Vinod,
> >
> >> -----Original Message-----
> >> From: Vinod Koul <vkoul@kernel.org>
> >> Sent: Thursday, November 25, 2021 10:41 AM
> >> To: Swapnil Kashinath Jakhade <sjakhade@cadence.com>
> >> Cc: kishon@ti.com; robh+dt@kernel.org; p.zabel@pengutronix.de; linux-
> >> phy@lists.infradead.org; linux-kernel@vger.kernel.org;
> >> devicetree@vger.kernel.org; Milind Parab <mparab@cadence.com>; a-
> >> govindraju@ti.com
> >> Subject: Re: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII
> >> PHY multilink configuration
> >>
> >> EXTERNAL MAIL
> >>
> >>
> >> On 24-11-21, 07:33, Swapnil Kashinath Jakhade wrote:
> >>
> >> > > so this is pcie->qsgmii ->ssc/external/internal ... ok
> >> > >
> >> > > > +				[NO_SSC] =
> >> > > &pcie_100_no_ssc_plllc_cmn_vals,
> >> > > > +				[EXTERNAL_SSC] =
> >> > > &pcie_100_ext_ssc_plllc_cmn_vals,
> >> > > > +				[INTERNAL_SSC] =
> >> > > &pcie_100_int_ssc_plllc_cmn_vals,
> >> > > > +			},
> >> > > >  		},
> >> > > >  		[TYPE_USB] = {
> >> > > >  			[TYPE_NONE] = {
> >> > > >  				[EXTERNAL_SSC] =
> >> > > &usb_100_ext_ssc_cmn_vals,
> >> > > >  			},
> >> > > >  		},
> >> > > > +		[TYPE_QSGMII] = {
> >> > > > +			[TYPE_PCIE] = {
> >> > >
> >> > > now it is reverse! qsgmii -> pcie -> ... why?
> >> > >
> >> > > what is meant by pcie->qsgmii and qsgmii-> pcie?
> >> > >
> >> >
> >> > Multi-protocol configuration is done in 2 phases, each for one protocol.
> >> > e.g. for PCIe + QSGMII case,
> >> > [TYPE_PCIE][TYPE_QSGMII] will configure common and lane registers
> >> > for PCIe and [TYPE_QSGMII][TYPE_PCIE] will configure common and lane
> >> registers for QSGMII.
> >>
> >> Then it should be always common + protocol or protocol + common, not
> >> both please! Pls make an order and stick to it everywhere... If that
> >> is not possible, I would like to understand why
> >>
> >
> >Could you please elaborate what do you mean by " common + protocol or
> >protocol + common, not both please!"?
> >The order is same everywhere which is common + lane configuration for
> >protocol 1 and then for protocol 2. For multiprotocol case, PHY configuration is
> >based on which protocols are operating simultaneously. So e.g.
> >[TYPE_QSGMII][TYPE_PCIE] -> QSGMII configuration when other protocol is
> >PCIe Which might be different than [TYPE_QSGMII][TYPE_*] -> QSGMII
> >configuration with other protocol.
> >
> >Thanks & regards,
> >Swapnil
> >
> >> --
> >> ~Vinod

-- 
~Vinod