Date:   Thu, 9 Dec 2021 15:49:06 +0100
From:   Wolfram Sang <wsa@kernel.org>
To:     Sam Protsenko <semen.protsenko@linaro.org>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
        Jaewon Kim <jaewon02.kim@samsung.com>,
        Chanho Park <chanho61.park@samsung.com>,
        David Virag <virag.david003@gmail.com>,
        Youngmin Nam <youngmin.nam@samsung.com>,
        Arnd Bergmann <arnd@arndb.de>, linux-i2c@vger.kernel.org,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v3] i2c: exynos5: Add bus clock support
Message-ID: <YbIXYinx3J9cfYrr@ninjato>
Mail-Followup-To: Wolfram Sang <wsa@kernel.org>,
        Sam Protsenko <semen.protsenko@linaro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
        Jaewon Kim <jaewon02.kim@samsung.com>,
        Chanho Park <chanho61.park@samsung.com>,
        David Virag <virag.david003@gmail.com>,
        Youngmin Nam <youngmin.nam@samsung.com>,
        Arnd Bergmann <arnd@arndb.de>, linux-i2c@vger.kernel.org,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org
References: <20211209140313.14926-1-semen.protsenko@linaro.org>
MIME-Version: 1.0
Content-Type: multipart/signed; micalg=pgp-sha512;
        protocol="application/pgp-signature"; boundary="DEQvb2BR+ftSzNBZ"
Content-Disposition: inline
In-Reply-To: <20211209140313.14926-1-semen.protsenko@linaro.org>
Precedence: bulk


--DEQvb2BR+ftSzNBZ
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable

On Thu, Dec 09, 2021 at 04:03:13PM +0200, Sam Protsenko wrote:
> In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a
> part of USIv2 block, there are two clocks provided to HSI2C controller:
>   - PCLK: bus clock (APB), provides access to register interface
>   - IPCLK: operating IP-core clock; SCL is derived from this one
>=20
> Both clocks have to be asserted for HSI2C to be functional in that case.
>=20
> Add code to obtain and enable/disable PCLK in addition to already
> handled operating clock. Make it optional though, as older Exynos SoC
> variants only have one HSI2C clock.
>=20
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> Reviewed-by: Chanho Park <chanho61.park@samsung.com>

Applied to for-next, thanks!


--DEQvb2BR+ftSzNBZ
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iQIzBAABCgAdFiEEOZGx6rniZ1Gk92RdFA3kzBSgKbYFAmGyF2IACgkQFA3kzBSg
KbadixAAth7qW3Rnrv1+LKeOBXDyB7R6MKGLgThiQop8aOkeCFKx6EEDoCvwR63l
MC6zQlref+iiRUFzRX0AERM0vZN+q4qGXw6RQ+6V05mRmZ7hM3JHvMNtPwHHH7ET
8qbZDc1OBr/1CEZAwN0S49WRo4VlntZnv9fkZjGF2Ow2wyjMF+0MHsroHg+pqVTU
yLYApaLmUf+yGD+0BYLsdKCgD995pv0SAy3aEpwGRXwncbYYGGwaGrIf2GRawiyo
iykjcH+6pjAJPVN1c4T1O+81htqfBYlytstXPNoYw+rrCeTIg5Rv2E51PLsHm+T5
71DQt4B1/W/ZTXgjW6UySt6N1YkISIvC32RrZM+bX2Nk/m9mdX8CooZRH+GklSHo
znfqQ5j2rLJfyTXYBGnJo8mA79eBbi0Xr8ln4+pYxYW9Gkl0DkZsX9JObvNaKhoM
JiWWhh6UXFKQTz00CoHawzQTE7Selopy9B469R03z+nATAqAr3KTnQSwy5+dUPVA
ScZT+uva4D7lWKT8CzFZDQFOakinkmGG5BnaEf5IEy4NLavkL5SR+sE3lj4iHEUJ
68Tlk0SRJGpQ47tRGHXaau/gNw5Y9n9klnEy3eyOPfnx/oWy7pNgm7ZofBBwtF0D
D1JjAWttjsNpJlbd5ja3sCuvVDCfnVwnB8vtIJ3IG77VBYI05YE=
=6qqn
-----END PGP SIGNATURE-----

--DEQvb2BR+ftSzNBZ--