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From:   Jim Mattson <jmattson@google.com>
Date:   Thu, 9 Dec 2021 16:54:29 -0800
Message-ID: <CALMp9eTtsMuEsimONp7TOjJ-uskwJBD-52kZzOefSKXeCwn_5A@mail.gmail.com>
Subject: Re: [PATCH v2 4/6] KVM: x86/pmu: Add pmc->intr to refactor kvm_perf_overflow{_intr}()
To:     Like Xu <like.xu.linux@gmail.com>
Cc:     Andi Kleen <ak@linux.intel.com>,
        Kim Phillips <kim.phillips@amd.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        Sean Christopherson <seanjc@google.com>,
        Vitaly Kuznetsov <vkuznets@redhat.com>,
        Wanpeng Li <wanpengli@tencent.com>,
        Joerg Roedel <joro@8bytes.org>, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org, Like Xu <likexu@tencent.com>
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On Thu, Dec 9, 2021 at 12:28 AM Like Xu <like.xu.linux@gmail.com> wrote:
>
> On 9/12/2021 12:25 pm, Jim Mattson wrote:
> >
> > Not your change, but if the event is counting anything based on
> > cycles, and the guest TSC is scaled to run at a different rate from
> > the host TSC, doesn't the initial value of the underlying hardware
> > counter have to be adjusted as well, so that the interrupt arrives
> > when the guest's counter overflows rather than when the host's counter
> > overflows?
>
> I've thought about this issue too and at least the Intel Specification
> did not let me down on this detail:
>
>         "The counter changes in the VMX non-root mode will follow
>         VMM's use of the TSC offset or TSC scaling VMX controls"

Where do you see this? I see similar text regarding TSC packets in the
section on Intel Processor Trace, but nothing about PMU counters
advancing at a scaled TSC frequency.

> Not knowing if AMD or the real world hardware
> will live up to this expectation and I'm pessimistic.
>
> cc Andi and Kim.
>