From:   Swapnil Kashinath Jakhade <sjakhade@cadence.com>
To:     Vinod Koul <vkoul@kernel.org>
CC:     "kishon@ti.com" <kishon@ti.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
        "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        Milind Parab <mparab@cadence.com>,
        "a-govindraju@ti.com" <a-govindraju@ti.com>
Subject: RE: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
 multilink configuration
Thread-Topic: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
 multilink configuration
Thread-Index: AQHXx2bHmQutwPZ9l0Sv3BSHrxD/16wQu9eAgAG6aaCAAXB/AIALkHAQgArg6oCAAWeOIA==
Date:   Fri, 10 Dec 2021 09:46:46 +0000
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Hi Vinod,

> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: Thursday, December 9, 2021 5:24 PM
> To: Swapnil Kashinath Jakhade <sjakhade@cadence.com>
> Cc: kishon@ti.com; robh+dt@kernel.org; p.zabel@pengutronix.de; linux-
> phy@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; Milind Parab <mparab@cadence.com>; a-
> govindraju@ti.com
> Subject: Re: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
> multilink configuration
>=20
> EXTERNAL MAIL
>=20
>=20
> On 02-12-21, 14:12, Swapnil Kashinath Jakhade wrote:
> > Hi Vinod,
> >
> > > -----Original Message-----
> > > From: Vinod Koul <vkoul@kernel.org>
> > > Sent: Thursday, November 25, 2021 10:41 AM
> > > To: Swapnil Kashinath Jakhade <sjakhade@cadence.com>
> > > Cc: kishon@ti.com; robh+dt@kernel.org; p.zabel@pengutronix.de;
> > > linux- phy@lists.infradead.org; linux-kernel@vger.kernel.org;
> > > devicetree@vger.kernel.org; Milind Parab <mparab@cadence.com>; a-
> > > govindraju@ti.com
> > > Subject: Re: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe +
> > > QSGMII PHY multilink configuration
> > >
> > > EXTERNAL MAIL
> > >
> > >
> > > On 24-11-21, 07:33, Swapnil Kashinath Jakhade wrote:
> > >
> > > > > so this is pcie->qsgmii ->ssc/external/internal ... ok
> > > > >
> > > > > > +				[NO_SSC] =3D
> > > > > &pcie_100_no_ssc_plllc_cmn_vals,
> > > > > > +				[EXTERNAL_SSC] =3D
> > > > > &pcie_100_ext_ssc_plllc_cmn_vals,
> > > > > > +				[INTERNAL_SSC] =3D
> > > > > &pcie_100_int_ssc_plllc_cmn_vals,
> > > > > > +			},
> > > > > >  		},
> > > > > >  		[TYPE_USB] =3D {
> > > > > >  			[TYPE_NONE] =3D {
> > > > > >  				[EXTERNAL_SSC] =3D
> > > > > &usb_100_ext_ssc_cmn_vals,
> > > > > >  			},
> > > > > >  		},
> > > > > > +		[TYPE_QSGMII] =3D {
> > > > > > +			[TYPE_PCIE] =3D {
> > > > >
> > > > > now it is reverse! qsgmii -> pcie -> ... why?
> > > > >
> > > > > what is meant by pcie->qsgmii and qsgmii-> pcie?
> > > > >
> > > >
> > > > Multi-protocol configuration is done in 2 phases, each for one prot=
ocol.
> > > > e.g. for PCIe + QSGMII case,
> > > > [TYPE_PCIE][TYPE_QSGMII] will configure common and lane registers
> > > > for PCIe and [TYPE_QSGMII][TYPE_PCIE] will configure common and
> > > > lane
> > > registers for QSGMII.
> > >
> > > Then it should be always common + protocol or protocol + common, not
> > > both please! Pls make an order and stick to it everywhere... If that
> > > is not possible, I would like to understand why
> >
> > Could you please elaborate what do you mean by " common + protocol or
> > protocol + common, not both please!"?
> > The order is same everywhere which is common + lane configuration for
> > protocol 1 and then for protocol 2. For multiprotocol case, PHY
> > configuration is based on which protocols are operating simultaneously.=
 So
> e.g.
> > [TYPE_QSGMII][TYPE_PCIE] -> QSGMII configuration when other protocol
> > is PCIe Which might be different than [TYPE_QSGMII][TYPE_*] -> QSGMII
> > configuration with other protocol.
>=20
> As I said I would like to understand what is the difference b/w
> [TYPE_QSGMII][TYPE_PCIE] & [TYPE_PCIE][TYPE_QSGMII] and why?
>=20

This logic is for implementing multi-link PHY configuration.
Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2=
 lanes.
Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1.
So in this case, PLLLC is used for PCIe and PLLLC1 is used for QSGMII and
PHY will be configured in two steps as described below.
1. For first step, phy_t1 =3D TYPE_PCIE and phy_t2 =3D TYPE_QSGMII
     So we select registers as
     [TYPE_PCIE][TYPE_QSGMII][ssc]:=20
              This will configure PHY registers associated for *PCIe* (i.e.=
 first protocol)
              involving PLLLC registers and registers for first 2 lanes of =
PHY.
2. In second step, the variables phy_t1 and phy_t2 are swapped. So now,
    phy_t1 =3D TYPE_QSGMII and phy_t2 =3D TYPE_PCIE. And we select register=
s as:
    [TYPE_QSGMII][TYPE_PCIE][ssc]:
             This will configure PHY registers associated for *QSGMII* (i.e=
. second protocol)
             involving PLLLC1 registers and registers for other 2 lanes of =
PHY.

This completes the PHY configuration for multilink operation.
Above approach enables dividing the large number of PHY register configurat=
ions
into protocol specific smaller groups.

Please let me know if it answers your question.

Thanks & regards,
Swapnil

> --
> ~Vinod