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From:   =?UTF-8?B?5ZGC6Iqz6aiw?= <wellslutw@gmail.com>
Date:   Fri, 10 Dec 2021 22:07:43 +0800
Message-ID: <CAFnkrskptpWwhKzBegUH8--sJJe5MJpJEnGSwQ2t1aj8i1CR2g@mail.gmail.com>
Subject: Re: [PATCH v3 1/2] dt-bindings: pinctrl: Add dt-bindings for Sunplus SP7021
To:     Linus Walleij <linus.walleij@linaro.org>
Cc:     linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
        robh+dt@kernel.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        Wells Lu <wells.lu@sunplus.com>,
        Dvorkin Dmitry <dvorkin@tibbo.com>
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Re-send this email because it was rejected due to the wrong email format!

Hi Linus,

Thank you very much for your review!

Please see my answers below:

> > Add dt-bindings header files and documentation for Sunplus SP7021 SoC.
> >
> > Signed-off-by: Wells Lu <wellslutw@gmail.com>
>
> > +patternProperties:
> > +  '-pins$':
> > +    if:
> > +      type: object
> > +    then:
> > +      description: |
> > +        A pinctrl node should contain at least one subnodes representing the
> > +        pins or function-pins group available on the machine. Each subnode
> > +        will list the pins it needs, and how they should be configured.
> > +
> > +        Pinctrl node's client devices use subnodes for desired pin
> > +        configuration. Client device subnodes use below standard properties.
>
> I don't understand this if type object stuff here, Rob, help...

I'll remove "if type object" stuff next patch since
pinctrl node has no properties with "-pins" suffix.
except sub nodes.


> > +      properties:
> > +        pins:
> > +          description: |
> > +            Define pins which are used by pinctrl node's client device.
> (...)
> > +          $ref: /schemas/types.yaml#/definitions/uint32-array
>
> Why can this not $ref the standard binings in
> Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml
>
> See for example
> Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml
> for a nice example of how to use this.
> Yours,
> Linus Walleij
The pins' types and control of SP7021 are a bit complex.
Let me explain:

SP7021 has 99 digital GPIO pins which are numbered from
GPIO 0 to 98. All are multiplexed with some special function
pins. There are 3 types special function pins:

(1) function-pins:
    For example, if control-field SPI_FLASH_SEL is set to 1,
    GPIO 83, 84, 86 and 87 will be pins of SPI-NOR flash.
    If it is set to 2, GPIO 76, 78, 79 and 81 will be pins of
    SPI-NOR flash.

    For example 2, if control-bit UA0_SEL is set to 1,
    GPIO 88 and 89 will be TX and RX pins of UART_0
    (UART channel 0).

    For example 3, if control-bit EMMC_SEL is set to 1,
    GPIO 72, 73, 74, 75, 76, 77, 78, 79, 80, 81 will be
    pins of an eMMC device.

    The driver defines properties "function" and "groups"
    to select this kind of pins-function.

(2) fully pin-mux pins:
    GPIO 8 to 71 are 'fully pin-mux' pins.
    Pins of peripherals of SP7021 (ex: UART_1, UART_2,
    UART_3, UART_4, I2C_0, I2C_1, ..., SPI_0, SPI_1, ...
    GPIO_INT0, GPIO_INT1, .., RMII_of_Ethernet, and etc.)
    can be set to any pins of fully pin-mux pins.

    EX1 (UART channel 1):
    If control-field UA1_TX_SEL is set to 3, TX pin of
    UART_1 will be routed to GPIO 10 (3 - 1 + 8 = 10)
    If control-field UA1_RX_SEL is set to 4, RX pin of
    UART_1 will be routed to GPIO 11 (4 - 1 + 8 = 11)
    If control-field UA1_RTS_SEL is set to 5, RTS pin of
    UART_1 will be routed to GPIO 12 (5 - 1 + 8 = 12)
    If control-field UA1_CTS_SEL is set to 6, CTS pin of
    UART_1 will be routed to GPIO 13 (6 - 1 + 8 = 13)

    EX2 (I2C channel 0):
    If control-field I2C0_CLK_SEL is set to 20, CLK pin
    of I2C_0 will be routed to GPIO 27 (20 - 1 + 8 = 27)
    If control-field I2C0_DATA_SEL is set to 21, DATA pin
    of I2C_0 will be routed to GPIO 28 (21 - 1 + 9 = 28)

    Totally, SP7021 has 120 peripheral pins. The
    peripheral pins can be routed to any of 64  'fully
     pin-mux' pins. So total combinations are:
           120 x 64 = 7680
     This is why we cannot enumerate all combinations.

(3) I/O processor pins
    SP7021 has a built-in I/O processor.
    Any GPIO pins (GPIO 0 to 98) can be set to pins of
    I/O processor.

Property 'pins' is defined as uint32 array. Each item
defines a pin as below:
Bit 32~24 defines GPIO number. Its range is 0 ~ 98.
Bit 23~16 defines types: digital GPIO pins (3), IO processor pins (2)
or fully pin-mux pins (1)
Bit 15~8 defines pins of peripherals which are defined in
'include/dt-binging/pinctrl/sppctl.h'.
Bit 7~0 defines types or initial-state of digital GPIO pins.


Best regards,
Wells