Message-ID: <29c8eeeb-2dee-6182-a2d3-90821cda975a@gmail.com>
Date:   Fri, 10 Dec 2021 22:04:50 +0200
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Subject: Re: [PATCH 2/2] arm64: dts: imx8mm: Add support for emtrion
 emCON-MX8M Mini
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To:     reinhold.mueller@emtrion.com, robh+dt@kernel.org
Cc:     shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de,
        festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, inux-arm-kernel@lists.infradead.org
References: <20211209120934.4815-1-reinhold.mueller@emtrion.com>
 <20211209120934.4815-3-reinhold.mueller@emtrion.com>
From:   Matti Vaittinen <mazziesaccount@gmail.com>
In-Reply-To: <20211209120934.4815-3-reinhold.mueller@emtrion.com>
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Hi dee Ho Reinhold,


On 12/9/21 14:09, reinhold.mueller@emtrion.com wrote:
> From: Reinhold Mueller <reinhold.mueller@emtrion.com>
> 
> This patch adds support for the emtrion GmbH emCON-MX8M Mini modules.
> They are available with NXP i.MX 8M Mini equipped with 2 or 4 GB Memory.
> 
> The devicetree imx8mm-emcon.dtsi is the common part providing all
> module components and the basic support for the SoC. The support for the
> avari baseboard in the developer-kit configuration is provided by the
> emcon-avari dts files.
> 
> Signed-off-by: Reinhold Mueller <reinhold.mueller@emtrion.com>
> ---
>   arch/arm64/boot/dts/freescale/Makefile        |   3 +-
>   .../boot/dts/freescale/imx8mm-emcon-avari.dts |  23 +
>   .../dts/freescale/imx8mm-emcon-avari.dtsi     | 141 ++++
>   .../boot/dts/freescale/imx8mm-emcon.dtsi      | 645 ++++++++++++++++++
>   4 files changed, 811 insertions(+), 1 deletion(-)
>   create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts
>   create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi
>   create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi
> 

> +&i2c3 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c3>;
> +	status = "okay";
> +
> +	bd71847:pmic@4b {
> +		compatible = "rohm,bd71847";
> +		reg = <0x4b>;
> +		pinctrl-0 = <&pinctrl_pmic>;
> +		interrupt-parent = <&gpio3>;
> +		interrupts = <2 GPIO_ACTIVE_LOW>;

I assume this should be IRQ_TYPE_LEVEL_LOW

Best Regards
	-- Matti Vaittinen