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Sun, 12 Dec 2021 01:56:31 +0000 From: "Tian, Kevin" To: Thomas Gleixner , Jason Gunthorpe CC: "Jiang, Dave" , Logan Gunthorpe , LKML , Bjorn Helgaas , Marc Zygnier , Alex Williamson , "Dey, Megha" , "Raj, Ashok" , "linux-pci@vger.kernel.org" , Greg Kroah-Hartman , Jon Mason , Allen Hubbe , "linux-ntb@googlegroups.com" , "linux-s390@vger.kernel.org" , Heiko Carstens , Christian Borntraeger , "x86@kernel.org" , "Rodel, Jorg" , "iommu@lists.linux-foundation.org" Subject: RE: [patch 21/32] NTB/msi: Convert to msi_on_each_desc() Thread-Topic: [patch 21/32] NTB/msi: Convert to msi_on_each_desc() Thread-Index: AQHX4y1VNaiO68omHEet2J9DWrVARKwa1YEAgAAp0QCAABreAIAAIi2AgAE8MoCAAAd1gIAACyoAgAAPcQCAADDDAIAAp1uAgABn9QCAACTxgIAAAdGAgAAbd4CAAA94gIAABpSAgAt9SoCAADlJAIAAgb+AgABGMACAAAc8gIAAE+oAgAAmHACAAFJ4oIAAem8AgABqWwCAANPscIAAWxoAgADV7aA= Date: Sun, 12 Dec 2021 01:56:31 +0000 Message-ID: References: <878rx480fk.ffs@tglx> <87sfv2yy19.ffs@tglx> <20211209162129.GS6385@nvidia.com> <878rwtzfh1.ffs@tglx> <20211209205835.GZ6385@nvidia.com> <8735n1zaz3.ffs@tglx> <87sfv1xq3b.ffs@tglx> <20211210123938.GF6385@nvidia.com> <87fsr0xp31.ffs@tglx> <875yrvwavf.ffs@tglx> In-Reply-To: <875yrvwavf.ffs@tglx> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL1PR11MB5271.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5382d6d1-7740-4aba-a189-08d9bd129e59 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Dec 2021 01:56:31.2265 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: HuIDCOJdFjarZFqQ8DWCUKqEi2Z/iX9oNs3EtMUjetsSeGkizPHBnXJReUIlzBRzYsaUzYfHs5FwA/ZUzI0rZw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3871 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Thomas Gleixner > Sent: Saturday, December 11, 2021 9:05 PM >=20 > Kevin, >=20 > On Sat, Dec 11 2021 at 07:44, Kevin Tian wrote: > >> From: Thomas Gleixner > >> On Fri, Dec 10 2021 at 08:39, Jason Gunthorpe wrote: > >> > It is clever, we don't have an vIOMMU that supplies vIR today, so by > >> > definition all guests are excluded and only bare metal works. > >> > >> Dammit. Now you spilled the beans. :) > > > > Unfortunately we do have that today. Qemu supports IR for > > both AMD and Intel vIOMMU. >=20 > can you point me to the code? >=20 > All I can find is drivers/iommu/virtio-iommu.c but I can't find anything > vIR related there. >=20 Well, virtio-iommu is a para-virtualized vIOMMU implementations. In reality there are also fully emulated vIOMMU implementations (e.g. Qemu fully emulates Intel/AMD/ARM IOMMUs). In those configurations the IR logic in existing iommu drivers just apply: drivers/iommu/intel/irq_remapping.c drivers/iommu/amd/iommu.c ... As I replied in another mail, the 1st vIR implementation was introduced to Qemu back to 2016: commit 1121e0afdcfa0cd40e36bd3acff56a3fac4f70fd Author: Peter Xu Date: Thu Jul 14 13:56:13 2016 +0800 x86-iommu: introduce "intremap" property Adding one property for intel-iommu devices to specify whether we shoul= d support interrupt remapping. By default, IR is disabled. To enable it, we should use (take Intel IOMMU as example): -device intel_iommu,intremap=3Don This property can be shared by Intel and future AMD IOMMUs. Signed-off-by: Peter Xu Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Thanks Kevin