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References: <20211107074200.18911-1-sergio.paracuellos@gmail.com>
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From:   Sergio Paracuellos <sergio.paracuellos@gmail.com>
Date:   Mon, 13 Dec 2021 13:00:17 +0100
Message-ID: <CAMhs-H81xnaFqgTJT3jiNy_BBCuHhrA-t0A+0wMnp5Y0kFjGUQ@mail.gmail.com>
Subject: Re: [PATCH v5 0/4] clk: ralink: make system controller a reset provider
To:     "open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Cc:     linux-kernel <linux-kernel@vger.kernel.org>,
        Stephen Boyd <sboyd@kernel.org>,
        John Crispin <john@phrozen.org>, linux-staging@lists.linux.dev,
        Greg KH <gregkh@linuxfoundation.org>,
        NeilBrown <neil@brown.name>
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Precedence: bulk

Hi Stephen,

On Sun, Nov 7, 2021 at 8:42 AM Sergio Paracuellos
<sergio.paracuellos@gmail.com> wrote:
>
> Hi all,
>
> This patch series add minimal change to provide mt7621 resets properly
> defining them in the 'mediatek,mt7621-sysc' node which is the system
> controller of the SoC and is already providing clocks to the rest of
> the world.
>
> There is shared architecture code for all ralink platforms in 'reset.c'
> file located in 'arch/mips/ralink' but the correct thing to do to align
> hardware with software seems to define and add related reset code to the
> already mainlined clock driver.
>
> After this changes, we can get rid of the useless reset controller node
> in the device tree and use system controller node instead where the property
> '#reset-cells' has been added. Binding documentation for this nodeq has
> been updated with the new property accordly.
>
> This series also provide a bindings include header where all related
> reset bits for the MT7621 SoC are defined.
>
> Also, please take a look to this review [0] to understand better motivation
> for this series.
>
> Regarding the way of merging this:
>  - I'd like patches 1 and 4 which are related going through staging tree.
>  - The other two (patches 2 and 3) can perfectly go through the clock tree.
>
> Thanks in advance for your feedback.
>
> Changes in v5:
>  - Move platform driver init process into 'arch_initcall' to be sure the
>    rest of the world can get the resets available when needed (since PCIe
>    controller driver has been moved from staging into 'drivers/pci/controller'
>    is probed earlier and reset was not available so it was returning
>    -EPROBE_DEFER on firt try. Moving into 'arch_initcall' avoids the 'a bit
>    anoying' PCI first failed log trace.

Gentle ping on this series.

Thanks,
     Sergio Paracuellos

>
> Changes in v4:
>  - I sent wrong patch 3 accidentaly so now include the good version, sorry.
>
> Changes in v3:
>  - Collect Rob's Acked-by for patches 1 and 2.
>  - Rebase on the top of staging-next since there were already many
>    changes there and PATCH 4 of the series didn't apply cleanly.
>
> Changes in v2:
>  - Address review comments of Dan Carpenter [1]:
>  + Avoid 'inline' in function definition.
>  + Return proper error codes (-EINVAL) instead of '-1'.
>  + Make use of 'devm_kzalloc' instead of 'kzalloc'.
>
> Best regards,
>    Sergio Paracuellos
>
> Sergio Paracuellos (4):
>   dt-bindings: reset: add dt binding header for Mediatek MT7621 resets
>   dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
>   clk: ralink: make system controller node a reset provider
>   staging: mt7621-dts: align resets with binding documentation
>
>  .../bindings/clock/mediatek,mt7621-sysc.yaml  | 12 +++
>  drivers/clk/ralink/clk-mt7621.c               | 86 ++++++++++++++++++-
>  drivers/staging/mt7621-dts/mt7621.dtsi        | 25 +++---
>  include/dt-bindings/reset/mt7621-reset.h      | 37 ++++++++
>  4 files changed, 145 insertions(+), 15 deletions(-)
>  create mode 100644 include/dt-bindings/reset/mt7621-reset.h
>
> --
> 2.33.0
>