Subject: Re: [PATCH v5 3/5] pinctrl: qcom: Extract chip specific LPASS LPI
 code
To:     Andy Shevchenko <andy.shevchenko@gmail.com>
CC:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Liam Girdwood <lgirdwood@gmail.com>,
        Mark Brown <broonie@kernel.org>,
        Rob Herring <robh+dt@kernel.org>, <plai@codeaurora.org>,
        Banajit Goswami <bgoswami@codeaurora.org>,
        "Jaroslav Kysela" <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
        Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
        <rohitkr@codeaurora.org>, <linux-arm-msm@vger.kernel.org>,
        ALSA Development Mailing List <alsa-devel@alsa-project.org>,
        devicetree <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Stephen Boyd <swboyd@chromium.org>, <judyhsiao@chromium.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        Venkata Prasad Potturu <quic_potturu@quicinc.com>
References: <1638891339-21806-1-git-send-email-quic_srivasam@quicinc.com>
 <1638891339-21806-4-git-send-email-quic_srivasam@quicinc.com>
 <CAHp75Vd=47Tv9Sf+styPhxS2=O1H2KUDeKQXTULUYU5fDgGwwA@mail.gmail.com>
 <0f6621e5-f014-27c9-be8b-6c32ab994304@quicinc.com>
 <CAHp75VdL3hmr23CcJLDpvbHaKv5HrDZjmVQpCnRNmPM7nEx6WQ@mail.gmail.com>
From:   Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Organization: Qualcomm
Message-ID: <4bcfadd0-8abb-e9e9-ad18-a5b1d3d46308@quicinc.com>
Date:   Tue, 14 Dec 2021 22:52:08 +0530
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On 12/14/2021 10:46 PM, Andy Shevchenko wrote:
> On Tue, Dec 14, 2021 at 7:15 PM Srinivasa Rao Mandadapu
> <quic_srivasam@quicinc.com> wrote:
>> On 12/8/2021 11:58 AM, Andy Shevchenko wrote:
> ...
>
>>>> +#define NO_SLEW                                -1
>>> Naming sucks for the header.
>>>
>>> LPI_NO_SLEW ?
>> Actually it's already mainline code. Just these patches are
>> rearrangement of old code.
>>
>> still do you suggest to change?
> I would, but this means it should be in a separate change.
>
> ...
Yes. Will do it separate patch later.
>
>>>> +struct lpi_pingroup {
>>>> +       const char *name;
>>>> +       const unsigned int *pins;
>>>> +       unsigned int npins;
>>>> +       unsigned int pin;
>>>> +       /* Bit offset in slew register for SoundWire pins only */
>>>> +       int slew_offset;
>>>> +       unsigned int *funcs;
>>>> +       unsigned int nfuncs;
>>>> +};
>>> Are you going to convert this to use struct group_desc?
> Any comments on this? It sounds like further improvements.
Actually this also needs as separate patch. these patches will do as 
separate series.
>