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References: <3dd2473a-00ca-4c62-e17f-9392cf74cda4@intel.com> <20211214113653.4631-1-pshete@nvidia.com>
In-Reply-To: <20211214113653.4631-1-pshete@nvidia.com>
From:   Ulf Hansson <ulf.hansson@linaro.org>
Date:   Tue, 14 Dec 2021 21:37:01 +0100
Message-ID: <CAPDyKFq1NMXrMw0Dn6T7-0J1C4QdNoi4dUfnB5=zMQKeyQoAdQ@mail.gmail.com>
Subject: Re: [PATCH v4] mmc: sdhci-tegra: Fix switch to HS400ES mode
To:     Prathamesh Shete <pshete@nvidia.com>
Cc:     adrian.hunter@intel.com, thierry.reding@gmail.com,
        jonathanh@nvidia.com, p.zabel@pengutronix.de,
        linux-mmc@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org, anrao@nvidia.com,
        smangipudi@nvidia.com
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Tue, 14 Dec 2021 at 12:36, Prathamesh Shete <pshete@nvidia.com> wrote:
>
> When CMD13 is sent after switching to HS400ES mode, the bus
> is operating at either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR.
> To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI
> interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
> controller CAR clock and the interface clock are rate matched.
>
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>

Applied for fixes and by adding a fixes and a stable tag, thanks!

Fixes: dfc9700cef77 ("mmc: tegra: Implement HS400 enhanced strobe")

Kind regards
Uffe


> ---
>  drivers/mmc/host/sdhci-tegra.c | 43 ++++++++++++++++++++--------------
>  1 file changed, 26 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index 387ce9cdbd7c..7be6674eebd5 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -354,23 +354,6 @@ static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
>         }
>  }
>
> -static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
> -                                             struct mmc_ios *ios)
> -{
> -       struct sdhci_host *host = mmc_priv(mmc);
> -       u32 val;
> -
> -       val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
> -
> -       if (ios->enhanced_strobe)
> -               val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
> -       else
> -               val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
> -
> -       sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
> -
> -}
> -
>  static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
>  {
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> @@ -791,6 +774,32 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
>         }
>  }
>
> +static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
> +                                             struct mmc_ios *ios)
> +{
> +       struct sdhci_host *host = mmc_priv(mmc);
> +       u32 val;
> +
> +       val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
> +
> +       if (ios->enhanced_strobe) {
> +               val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
> +               /*
> +                * When CMD13 is sent from mmc_select_hs400es() after
> +                * switching to HS400ES mode, the bus is operating at
> +                * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR.
> +                * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI
> +                * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
> +                * controller CAR clock and the interface clock are rate matched.
> +                */
> +               tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR);
> +       } else {
> +               val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
> +       }
> +
> +       sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
> +}
> +
>  static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
>  {
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> --
> 2.17.1
>