From:   Dejia Shang <dejia.shang@armchina.com>
To:     gregkh@linuxfoundation.org, robh+dt@kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        devicetree@vger.kernel.org
Cc:     dejia.shang@armchina.com, toby.shang@armchina.com
Subject: [PATCH 3/4] dt-bindings: add vendor-prefix and documentation for Zhouyi NPU
Date:   Wed, 15 Dec 2021 18:36:08 +0800
Message-Id: <20211215103609.9268-4-dejia.shang@armchina.com>
In-Reply-To: <20211215103609.9268-1-dejia.shang@armchina.com>
References: <20211215103609.9268-1-dejia.shang@armchina.com>
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To enable this NPU IP in Arm-Linux system, SoC vendors should
write devicetree files as documented.

Signed-off-by: Dejia Shang <dejia.shang@armchina.com>
---
 .../bindings/misc/armchina,zhouyi-npu.yaml    | 57 +++++++++++++++++++
 .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
 2 files changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/armchina,zhouyi-=
npu.yaml

diff --git a/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yam=
l b/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
new file mode 100644
index 000000000000..d3fdea101114
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/armchina,zhouyi-npu.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: ArmChina Zhouyi NPU bindings
+
+maintainers:
+  - Dejia Shang <dejia.shang@armchina.com>
+
+description: |
+  Armchina AI accelerator IP - Zhouyi NPU
+
+properties:
+  compatible:
+    items:
+      - const: armchina,zhouyi-v1
+      - const: armchina,zhouyi-v2
+      - const: armchina,zhouyi
+
+  reg:
+    maxItems: 1
+
+  memory-region:
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    reserved-memory {
+                #address-cells =3D <2>;
+                #size-cells =3D <2>;
+                ranges;
+
+                aipu_ddr_reserved: aipu-shmem@0xA0000000 {
+                        compatible =3D "shared-dma-pool";
+                        no-map;
+                        reg =3D <0x0 0xA0000000 0x0 0x4000000>;
+                };
+    };
+
+    aipu0@0x64000000 {
+                compatible =3D "armchina,zhouyi";
+                reg =3D <0x0 0x64000000 0x0 0x1000>;
+                memory-region=3D<&aipu_ddr_reserved>;
+                interrupts =3D <0 168 1>;
+    };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum=
entation/devicetree/bindings/vendor-prefixes.yaml
index 66d6432fd781..4b1865d92455 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -123,6 +123,8 @@ patternProperties:
     description: ARM Ltd.
   "^armadeus,.*":
     description: ARMadeus Systems SARL
+  "^armchina,.*":
+    description: Arm Technology (China) Co., Ltd.
   "^arrow,.*":
     description: Arrow Electronics
   "^artesyn,.*":
--
2.17.1

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