Date:   Wed, 15 Dec 2021 19:07:17 +0100
From:   Borislav Petkov <bp@alien8.de>
To:     William Roche <william.roche@oracle.com>
Cc:     Yazen Ghannam <yazen.ghannam@amd.com>, linux-edac@vger.kernel.org,
        linux-kernel@vger.kernel.org, mchehab@kernel.org,
        tony.luck@intel.com, james.morse@arm.com, rric@kernel.org,
        Smita.KoralahalliChannabasappa@amd.com
Subject: Re: [PATCH v2 2/2] EDAC/amd64: Add new register offset support and
 related changes
Message-ID: <Ybou1VTJ8oced4Ge@zn.tnic>
References: <20211215155309.2711917-1-yazen.ghannam@amd.com>
 <20211215155309.2711917-3-yazen.ghannam@amd.com>
 <d327bbfe-a3c0-9b26-569d-43e17dba126d@oracle.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
In-Reply-To: <d327bbfe-a3c0-9b26-569d-43e17dba126d@oracle.com>
Precedence: bulk

On Wed, Dec 15, 2021 at 05:32:27PM +0100, William Roche wrote:
> > @@ -2174,8 +2215,13 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
> >   	 * There is one mask per DIMM, and two Chip Selects per DIMM.
> >   	 *	CS0 and CS1 -> DIMM0
> >   	 *	CS2 and CS3 -> DIMM1
> > +	 *
> > +	 *	Systems with newer register layout have one mask per Chip Select.
> 
> Just a question about this comment: Can it be translated into this ?
> 
> +	 * Except on systems with newer register layout where we have one Chip Select per DIMM.

Sure, but without the "we":

	...
	* On systems with the newer register layout there is one Chip Select per DIMM.
	*/

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette