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[81.172.62.207]) by smtp.gmail.com with ESMTPSA id s8sm3291108wra.9.2021.12.15.11.33.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Dec 2021 11:33:03 -0800 (PST) Message-ID: Date: Wed, 15 Dec 2021 20:33:02 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Subject: Re: [PATCH v8 2/2] arm64: dts: mediatek: add basic mt7986 support Content-Language: en-US To: Sam Shih , Rob Herring , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , Sean Wang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Cc: John Crispin , Ryder Lee References: <20211122123222.8016-1-sam.shih@mediatek.com> <20211122123222.8016-3-sam.shih@mediatek.com> From: Matthias Brugger In-Reply-To: <20211122123222.8016-3-sam.shih@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/11/2021 13:32, Sam Shih wrote: > Add basic chip support for Mediatek mt7986, include > basic uart nodes, rng node and watchdog node. > > Add cpu node, timer node, gic node, psci and reserved-memory node > for ARM Trusted Firmware. > > Signed-off-by: Sam Shih > > --- > v8: removed debug bootargs > v7: added memory node back to dts > v6: removed clock and pinctrl node, to separate basic part into a single > patch series > > Original thread: > https://lore.kernel.org/all/20211004124155.1404-1-sam.shih@mediatek.com/ > > v5: follow reviewr's comment: removed clock freqency node in timer due to > we have set CNTFRQ_EL0 in ATF firmware, and also corrected GICD range > v4: added missing gic register bases, and fixed range of GICR > v3: used the stdout-path instead of console=ttyS0 > v2: modified clock and uart node due to clock driver updated > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 37 +++++ > arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 148 +++++++++++++++++++ > 3 files changed, 186 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index 4f68ebed2e31..e6c3a73b9e4a 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts > new file mode 100644 > index 000000000000..6911862390d7 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts > @@ -0,0 +1,37 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2021 MediaTek Inc. > + * Author: Sam.Shih > + */ > + > +/dts-v1/; > +#include "mt7986a.dtsi" > + > +/ { > + model = "MediaTek MT7986a RFB"; > + compatible = "mediatek,mt7986a-rfb"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory { > + reg = <0 0x40000000 0 0x40000000>; Should be: memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; Please send a follow-up patch for that. Regards, Matthias > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > + > +&uart1 { > + status = "okay"; > +}; > + > +&uart2 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > new file mode 100644 > index 000000000000..77906839cc85 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > @@ -0,0 +1,148 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2021 MediaTek Inc. > + * Author: Sam.Shih > + */ > + > +#include > +#include > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + system_clk: dummy40m { > + compatible = "fixed-clock"; > + clock-frequency = <40000000>; > + #clock-cells = <0>; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x0>; > + #cooling-cells = <2>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x1>; > + #cooling-cells = <2>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x2>; > + #cooling-cells = <2>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + enable-method = "psci"; > + compatible = "arm,cortex-a53"; > + reg = <0x3>; > + #cooling-cells = <2>; > + }; > + }; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ > + secmon_reserved: secmon@43000000 { > + reg = <0 0x43000000 0 0x30000>; > + no-map; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + ; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x10000>, /* GICD */ > + <0 0x0c080000 0 0x80000>, /* GICR */ > + <0 0x0c400000 0 0x2000>, /* GICC */ > + <0 0x0c410000 0 0x1000>, /* GICH */ > + <0 0x0c420000 0 0x2000>; /* GICV */ > + interrupts = ; > + }; > + > + watchdog: watchdog@1001c000 { > + compatible = "mediatek,mt7986-wdt", > + "mediatek,mt6589-wdt"; > + reg = <0 0x1001c000 0 0x1000>; > + interrupts = ; > + #reset-cells = <1>; > + status = "disabled"; > + }; > + > + trng: trng@1020f000 { > + compatible = "mediatek,mt7986-rng", > + "mediatek,mt7623-rng"; > + reg = <0 0x1020f000 0 0x100>; > + clocks = <&system_clk>; > + clock-names = "rng"; > + status = "disabled"; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt7986-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x400>; > + interrupts = ; > + clocks = <&system_clk>; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt7986-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x400>; > + interrupts = ; > + clocks = <&system_clk>; > + status = "disabled"; > + }; > + > + uart2: serial@11004000 { > + compatible = "mediatek,mt7986-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11004000 0 0x400>; > + interrupts = ; > + clocks = <&system_clk>; > + status = "disabled"; > + }; > + > + }; > + > +}; >