Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84C41C4332F for ; Thu, 16 Dec 2021 06:41:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234161AbhLPGlC (ORCPT ); Thu, 16 Dec 2021 01:41:02 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:26402 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234142AbhLPGk7 (ORCPT ); Thu, 16 Dec 2021 01:40:59 -0500 Received: from epcas1p4.samsung.com (unknown [182.195.41.48]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20211216064057epoutp04d4e242518c83dbe8c55065754e259611~BKQj_PHpx0708007080epoutp04Q for ; Thu, 16 Dec 2021 06:40:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20211216064057epoutp04d4e242518c83dbe8c55065754e259611~BKQj_PHpx0708007080epoutp04Q DKIM-Signature: v=1; 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Thu, 16 Dec 2021 06:40:41 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20211216064041epsmtrp263fdc7108d08ee6489234973cce136ac~BKQVEATVL1529315293epsmtrp2y; Thu, 16 Dec 2021 06:40:41 +0000 (GMT) X-AuditID: b6c32a38-93fff700000255ac-7a-61badf1db537 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id F9.ED.29871.96FDAB16; Thu, 16 Dec 2021 15:40:41 +0900 (KST) Received: from [10.113.221.102] (unknown [10.113.221.102]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20211216064041epsmtip236a8879ff754e1914b69e5ecb20dea91~BKQUw1W9Y3224732247epsmtip2b; Thu, 16 Dec 2021 06:40:41 +0000 (GMT) Subject: Re: [PATCH 1/7] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks To: Sam Protsenko , Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Jaewon Kim , Chanho Park , David Virag , Youngmin Nam , Tomasz Figa , Michael Turquette , Stephen Boyd , Linus Walleij , Daniel Palmer , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org From: Chanwoo Choi Organization: Samsung Electronics Message-ID: Date: Thu, 16 Dec 2021 16:03:42 +0900 User-Agent: Mozilla/5.0 (X11; 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charset="utf-8" X-Sendblock-Type: SVC_REQ_APPROVE CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20211215160912epcas1p25e6c9a95aee33d6de8c73c892e524220 References: <20211215160906.17451-1-semen.protsenko@linaro.org> <20211215160906.17451-2-semen.protsenko@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/16/21 1:09 AM, Sam Protsenko wrote: > System Register is used to configure system behavior, like USI protocol, > etc. SYSREG clocks should be provided to corresponding syscon nodes, to > make it possible to modify SYSREG registers. > > While at it, add also missing PMU and GPIO clocks, which looks necessary > and might be needed for corresponding Exynos850 features soon. > > Signed-off-by: Sam Protsenko > --- > include/dt-bindings/clock/exynos850.h | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h > index 8aa5e82af0d3..0b6a3c6a7c90 100644 > --- a/include/dt-bindings/clock/exynos850.h > +++ b/include/dt-bindings/clock/exynos850.h > @@ -82,7 +82,10 @@ > #define CLK_GOUT_I3C_PCLK 19 > #define CLK_GOUT_I3C_SCLK 20 > #define CLK_GOUT_SPEEDY_PCLK 21 > -#define APM_NR_CLK 22 > +#define CLK_GOUT_GPIO_ALIVE_PCLK 22 > +#define CLK_GOUT_PMU_ALIVE_PCLK 23 > +#define CLK_GOUT_SYSREG_APM_PCLK 24 > +#define APM_NR_CLK 25 > > /* CMU_CMGP */ > #define CLK_RCO_CMGP 1 > @@ -99,7 +102,8 @@ > #define CLK_GOUT_CMGP_USI0_PCLK 12 > #define CLK_GOUT_CMGP_USI1_IPCLK 13 > #define CLK_GOUT_CMGP_USI1_PCLK 14 > -#define CMGP_NR_CLK 15 > +#define CLK_GOUT_SYSREG_CMGP_PCLK 15 > +#define CMGP_NR_CLK 16 > > /* CMU_HSI */ > #define CLK_MOUT_HSI_BUS_USER 1 > @@ -167,7 +171,9 @@ > #define CLK_GOUT_MMC_EMBD_SDCLKIN 10 > #define CLK_GOUT_SSS_ACLK 11 > #define CLK_GOUT_SSS_PCLK 12 > -#define CORE_NR_CLK 13 > +#define CLK_GOUT_GPIO_CORE_PCLK 13 > +#define CLK_GOUT_SYSREG_CORE_PCLK 14 > +#define CORE_NR_CLK 15 > > /* CMU_DPU */ > #define CLK_MOUT_DPU_USER 1 > Acked-by: Chanwoo Choi -- Best Regards, Chanwoo Choi Samsung Electronics