Date:   Thu, 16 Dec 2021 19:21:47 +0000
From:   Yazen Ghannam <yazen.ghannam@amd.com>
To:     William Roche <william.roche@oracle.com>
Cc:     Borislav Petkov <bp@alien8.de>, linux-edac@vger.kernel.org,
        linux-kernel@vger.kernel.org, mchehab@kernel.org,
        tony.luck@intel.com, james.morse@arm.com, rric@kernel.org,
        Smita.KoralahalliChannabasappa@amd.com
Subject: Re: [PATCH v2 2/2] EDAC/amd64: Add new register offset support and
 related changes
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On Thu, Dec 16, 2021 at 07:43:55PM +0100, William Roche wrote:
...
> From what I understand, future systems would still support the same number
> of dimms per UMC (2), the same number of Chip Select (2 per dimm), the only
> thing that changes is the number of Address Mask registers (going from 2 per
> UMC? to? 4 per UMC).
> 
> So I'm confused, we deduce 'dimm' from csrow_nr, which would be in fact the
> Chip Select *masks* number (cs_mask_nr from the dbam_to_cs signature in
> struct low_ops), so why are we saying and dimm=csrow_nr in the case of the
> new layout, but dimm = csrow_nr / 2 in the case on the standard layout ?
> 
> Should we indicate what this 'dimm' value really is ?
> 
> Sorry if I'm missing something very obvious here.
>

That's fair. I can rework the patch to explicitly differentiate between "dimm"
and "cs_mask_nr" here.

I think this would resolve an issue in a later debug print statement that
includes the csrow_nr and dimm.

Thanks,
Yazen