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([2001:b07:add:ec09:c399:bc87:7b6c:fb2a]) by smtp.googlemail.com with ESMTPSA id m6sm8866287wrp.34.2021.12.17.00.28.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Dec 2021 00:28:06 -0800 (PST) Message-ID: <3c5472f4-44ce-9ba8-4dbc-967ea377ae10@redhat.com> Date: Fri, 17 Dec 2021 09:28:00 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Subject: Re: [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits Content-Language: en-US To: Anup Patel , Shuah Khan , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Albert Ou , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org References: <20211129075451.418122-1-anup.patel@wdc.com> <20211129075451.418122-3-anup.patel@wdc.com> From: Paolo Bonzini In-Reply-To: <20211129075451.418122-3-anup.patel@wdc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/29/21 08:54, Anup Patel wrote: > The number of GPA bits supported for a RISC-V Guest/VM is based on the > MMU mode used by the G-stage translation. The KVM RISC-V will detect and > use the best possible MMU mode for the G-stage in kvm_arch_init(). > > We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by > the KVM userspace to get the number of GPA (guest physical address) bits > supported for a Guest/VM. > > Signed-off-by: Anup Patel > --- > arch/riscv/include/asm/kvm_host.h | 1 + > arch/riscv/kvm/mmu.c | 5 +++++ > arch/riscv/kvm/vm.c | 3 +++ > include/uapi/linux/kvm.h | 1 + > 4 files changed, 10 insertions(+) > > diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h > index 37589b953bcb..ae5d238607fe 100644 > --- a/arch/riscv/include/asm/kvm_host.h > +++ b/arch/riscv/include/asm/kvm_host.h > @@ -221,6 +221,7 @@ void kvm_riscv_stage2_free_pgd(struct kvm *kvm); > void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu); > void kvm_riscv_stage2_mode_detect(void); > unsigned long kvm_riscv_stage2_mode(void); > +int kvm_riscv_stage2_gpa_size(void); > > void kvm_riscv_stage2_vmid_detect(void); > unsigned long kvm_riscv_stage2_vmid_bits(void); > diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c > index 9ffd0255af43..9b6d6465094f 100644 > --- a/arch/riscv/kvm/mmu.c > +++ b/arch/riscv/kvm/mmu.c > @@ -760,3 +760,8 @@ unsigned long kvm_riscv_stage2_mode(void) > { > return stage2_mode >> HGATP_MODE_SHIFT; > } > + > +int kvm_riscv_stage2_gpa_size(void) > +{ > + return stage2_gpa_bits; > +} > diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c > index fb18af34a4b5..6f959639ec45 100644 > --- a/arch/riscv/kvm/vm.c > +++ b/arch/riscv/kvm/vm.c > @@ -82,6 +82,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) > case KVM_CAP_NR_MEMSLOTS: > r = KVM_USER_MEM_SLOTS; > break; > + case KVM_CAP_VM_GPA_BITS: > + r = kvm_riscv_stage2_gpa_size(); > + break; > default: > r = 0; > break; > diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h > index 1daa45268de2..469f05d69c8d 100644 > --- a/include/uapi/linux/kvm.h > +++ b/include/uapi/linux/kvm.h > @@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt { > #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204 > #define KVM_CAP_ARM_MTE 205 > #define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206 > +#define KVM_CAP_VM_GPA_BITS 207 > > #ifdef KVM_CAP_IRQ_ROUTING > > This is nice and other architectures could support it. Paolo