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From:   Daniel Palmer <daniel@0x0f.com>
Date:   Fri, 17 Dec 2021 18:00:00 +0900
Message-ID: <CAFr9PXkvJzpFU5x=syR8dXwOuLXPurQoTnDEvmJ-+FrWn5F+ZA@mail.gmail.com>
Subject: Re: [PATCH v2 2/6] clocksource: msc313e: Add support for
 ssd20xd-based platforms
To:     Romain Perier <romain.perier@gmail.com>
Cc:     Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Russell King <linux@armlinux.org.uk>,
        DTML <devicetree@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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Hi Romain,

On Fri, 17 Dec 2021 at 03:18, Romain Perier <romain.perier@gmail.com> wrote:
>
> Hi Daniel,
>
> What do you think about the following description ?  :  "
>     clocksource: msc313e: Add support for ssd20xd-based platforms
>

>
>     Signed-off-by: Romain Perier <romain.perier@gmail.com>

I looked at the disassembly of the bootrom again and it doesn't look
like it's set there.
I think it's the hardware default for the register.

I'm thinking something like this:

On SSD20X family SoCs the timers are connected to a 432MHz clock
instead of 12MHz that all the previous chips used.
There is no way to reduce or divide these clocks in the clktree yet as
we don't know exactly where the 432MHz clock comes from but it's
enabled at boot.

The SSD20X timers have an input clock divider within the timer itself
to configure the frequency.
timer0 is preconfigured at power up to run at 12MHz so it is backwards
compatible and doesn't need special handling right now.
timer1 and timer2 run at 432Mhz at power up so are not backward compatible.

This commit adds support for the input clock divider register and sets
timer1 and timer2 to run at 48Mhz for clockevents.

Cheers,

Daniel