From:   Mauro Carvalho Chehab <mchehab@kernel.org>
To:     Wei Xu <xuwei5@hisilicon.com>, Rob Herring <robh+dt@kernel.org>
Cc:     Mauro Carvalho Chehab <mchehab+huawei@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-usb@vger.kernel.org,
        Mauro Carvalho Chehab <mchehab@kernel.org>
Subject: [PATCH v2 3/7] dt-bindings: usb: hisilicon,hi3670-dwc3: add binding for Kirin970
Date:   Fri, 17 Dec 2021 11:12:47 +0100
Message-Id: <03023825dafd0c9ae3f99e650e14137f290bb377.1639735742.git.mchehab@kernel.org>
In-Reply-To: <cover.1639735742.git.mchehab@kernel.org>
References: <cover.1639735742.git.mchehab@kernel.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

Add documentation for the DWC3 USB3 controller found on Kirin970
CPUs.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

See [PATCH v2 0/7] at: https://lore.kernel.org/all/cover.1639735742.git.mchehab@kernel.org/

 .../bindings/usb/hisilicon,hi3670-dwc3.yaml   | 105 ++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml

diff --git a/Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml b/Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml
new file mode 100644
index 000000000000..b38f3bfd9107
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/hisilicon,hi3670-dwc3.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/hisilicon,hi3670-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Kirin970 USB3 Controller
+
+maintainers:
+  - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
+
+description:
+  Bindings for the USB3 DWC3 controller present on Kirin970.
+
+properties:
+  compatible:
+    const: hisilicon,hi3670-dwc3
+
+  clocks:
+    maxItems: 4
+
+  clock-names:
+    items:
+      - const: abb
+      - const: hclk
+      - const: ref
+      - const: aclk
+
+  ranges: true
+
+  assigned-clocks:
+    maxItems: 1
+
+  assigned-clock-rates:
+    maxItems: 1
+
+  resets:
+    maxItems: 4
+
+  '#address-cells':
+    const: 2
+
+  '#size-cells':
+    const: 2
+
+# Required child node:
+
+patternProperties:
+  "^usb@[0-9a-f]+$":
+    $ref: snps,dwc3.yaml#
+
+required:
+  - compatible
+  - ranges
+  - clocks
+  - clock-names
+  - assigned-clocks
+  - assigned-clock-rates
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/hi3670-clock.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      usb3: dwc3 {
+        compatible = "hisilicon,hi3670-dwc3";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+
+        clocks = <&crg_ctrl HI3670_CLK_GATE_ABB_USB>,
+                 <&crg_ctrl HI3670_HCLK_GATE_USB3OTG>,
+                 <&crg_ctrl HI3670_CLK_GATE_USB3OTG_REF>,
+                 <&crg_ctrl HI3670_ACLK_GATE_USB3DVFS>;
+        clock-names = "abb",
+                      "hclk",
+                      "ref",
+                      "aclk";
+
+        assigned-clocks = <&crg_ctrl HI3670_ACLK_GATE_USB3DVFS>;
+        assigned-clock-rates = <238000000>;
+        resets = <&crg_rst 0x90 6>,
+                 <&crg_rst 0x90 7>,
+                 <&usb31_misc_rst 0xA0 8>,
+                 <&usb31_misc_rst 0xA0 9>;
+
+        dwc3: usb@ff100000 {
+          compatible = "snps,dwc3";
+          reg = <0x0 0xff100000 0x0 0x100000>;
+
+          interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>,
+                       <0 161 IRQ_TYPE_LEVEL_HIGH>;
+
+          phys = <&usb_phy>;
+          phy-names = "usb3-phy";
+        };
+      };
+    };
-- 
2.33.1