Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C27E9C43219 for ; Fri, 17 Dec 2021 10:29:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235020AbhLQK3J (ORCPT ); Fri, 17 Dec 2021 05:29:09 -0500 Received: from mout.kundenserver.de ([212.227.126.131]:43735 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230052AbhLQK3C (ORCPT ); Fri, 17 Dec 2021 05:29:02 -0500 Received: from mail-wm1-f50.google.com ([209.85.128.50]) by mrelayeu.kundenserver.de (mreue009 [213.165.67.97]) with ESMTPSA (Nemesis) id 1M3DBd-1mv9H70c1t-003cnj; Fri, 17 Dec 2021 11:29:00 +0100 Received: by mail-wm1-f50.google.com with SMTP id o19-20020a1c7513000000b0033a93202467so1275980wmc.2; Fri, 17 Dec 2021 02:28:59 -0800 (PST) X-Gm-Message-State: AOAM530TIWsOjX56L5p48423QNaanac0qxcA9nMJBgwtpgl1S2w4O6L5 dMonB9WfKEi4m4IpWug4Q3eDoYD3Zjvmh6/+d1c= X-Google-Smtp-Source: ABdhPJzt5zYuPDN2kyerQhSiMM2qDbHR33/fmfF5ts41gKt3J8mLkHRysVIEdlJk2pNUlh3mDSd/3MBFVv8V8UNy0j0= X-Received: by 2002:a05:600c:6d2:: with SMTP id b18mr2096113wmn.98.1639736939561; Fri, 17 Dec 2021 02:28:59 -0800 (PST) MIME-Version: 1.0 References: <20211215220538.4180616-1-Mr.Bossman075@gmail.com> <1360c4fe-4a09-a8a1-3224-7f1d4af59f6f@benettiengineering.com> <634e9304-2eba-4ea9-65ac-5d4f5d011b70@benettiengineering.com> In-Reply-To: <634e9304-2eba-4ea9-65ac-5d4f5d011b70@benettiengineering.com> From: Arnd Bergmann Date: Fri, 17 Dec 2021 11:28:43 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RESEND in plain-test] Re: [PATCH v5 0/9] Add initial support for the i.MXRTxxxx SoC family starting from i.IMXRT1050 SoC. To: Giulio Benetti Cc: Arnd Bergmann , Jesse Taube , NXP Linux Team , Michael Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Sascha Hauer , Fabio Estevam , Ulf Hansson , Dong Aisheng , Stefan Agner , Linus Walleij , gregkh , Olof Johansson , SoC Team , Russell King - ARM Linux , Abel Vesa , Adrian Hunter , Jiri Slaby , Nobuhiro Iwamatsu , linux-clk , DTML , Linux ARM , Linux Kernel Mailing List , linux-mmc , "open list:GPIO SUBSYSTEM" , "open list:SERIAL DRIVERS" , Vladimir Murzin Content-Type: text/plain; charset="UTF-8" X-Provags-ID: V03:K1:WK5VepgWAxnURy8YRejIh8hTkw5BVDQTSGj/3hPn3SfcZcCrTNG lyrjT7Khp69AhFY2gmWBqy8B7mI0u376qu/e8G+ii1vIN8sgfc/1+L3rjj94EI3UnaG0z57 RO+Pq9Xqvyn/wjbT7TA9Te2G/+YJro8CWVtmzVrYJxaS1Z5N6psweEF9CjLox9uW8fNy32M GbCTb7+MTwkGrVS+vq8ww== X-UI-Out-Filterresults: notjunk:1;V03:K0:lLY2FP303Ug=:MZPZYIsXwYO/ZM4ROB9bVL ek+5PS1T7DfV9tiQ87KICIi9k6x4nuPH98rqb0m7oJUEJWrPLc2ez8ADmiMGAyYwyC8pv1AAy xya0TCnN5uypyLGXuGqcxBeQcKTGk1FHhTaiW5o7ohDxUPljwJ/lnLJk1XlfmaFbJ+ffXmz3X n8KrmA2dUCShP1GgdHOZVG/09ZNaTw7t3VcQws87+YsdmR6tMyfOS0B4iMv2h0HqqdKg6EpNr 4C4VpPGy5Z1sc1fTDgaFrb+tfiFu88DMyb3gv0EU/6MpzBfBSa9RUQupHb4llGvYJL6sqQsIw M5bODNoegAojZzX9YZxk4DqT19BmGrsGEsvvp9EgOU4rd3+mq5etrOVaPre9w6YkJEuG9oSRP U9F+WsDgBJNkfoolfjYhu5Jz3Jim8au0jpykcloY6yE7iLL+CQ2H7Z27p1OyJidBRmZB1Yunn wDlOCeCCDsKpMisu6DMCIfzT+vwyA5+fyJ9RGWXOH0oSy4ar0+IawfV80JEMp7mjOvQu+eNir oO3OiwkaTYaDkPZ7muehPSYq0Po6AcHR4fA3H69wKOaIbq058nkE6Fi49b0d/cLymY/q6cfVV 4mzsltuA093tdpFohN4LP9Rk3Jb1Bq2lN1LdApMefoWcniNQDghB3pZ5J8XIXWUqRs2N7PX5o CWJ1F1IGni4qppXt7S1SD0jXlbNKuJ62jmwzE+R7VqLFp1zm3ruQ5/uncYdUf9Lcwkq8= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 17, 2021 at 10:54 AM Giulio Benetti wrote: > On 16/12/21 22:13, Arnd Bergmann wrote: > > > Vladimir has put some work into making Cortex-R work in the kernel, and > > he may have some other thoughts on this question. > > I'm curious if he has something specific to Cortex-R to tell. > > I've found that Cortex-R82 has a MMU: > https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r82 > but I can't find any SoC that uses it. Also, I don't know how many > people could use it honestly. R82 is fairly new, but I expect that we will see support in Linux in the future. Aside from having an MMU, it also 64-bit-only, so we'd treat it like a normal ARMv8-A core in arch/arm64. Arnd