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From:   Tim Harvey <tharvey@gateworks.com>
Date:   Fri, 17 Dec 2021 09:26:58 -0800
Message-ID: <CAJ+vNU1ZxAAasKT8j1sfcFz1pk8fyYjwOW6wqxYq_ur8+2MX_Q@mail.gmail.com>
Subject: Re: [RFC 0/5] arm64: imx8mm: Enable Hantro VPUs
To:     Nicolas Dufresne <nicolas@ndufresne.ca>
Cc:     Adam Ford <aford173@gmail.com>,
        Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>,
        linux-media <linux-media@vger.kernel.org>,
        Schrempf Frieder <frieder.schrempf@kontron.de>,
        Marek Vasut <marek.vasut@gmail.com>,
        Jagan Teki <jagan@amarulasolutions.com>,
        Adam Ford-BE <aford@beaconembedded.com>,
        cstevens@beaconembedded.com,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Mauro Carvalho Chehab <mchehab@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Heiko Stuebner <heiko@sntech.de>,
        Lucas Stach <l.stach@pengutronix.de>,
        Joakim Zhang <qiangqing.zhang@nxp.com>,
        Alice Guo <alice.guo@nxp.com>, Peng Fan <peng.fan@nxp.com>,
        "open list:HANTRO VPU CODEC DRIVER" 
        <linux-rockchip@lists.infradead.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        open list <linux-kernel@vger.kernel.org>,
        "open list:STAGING SUBSYSTEM" <linux-staging@lists.linux.dev>
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On Fri, Dec 17, 2021 at 9:13 AM Nicolas Dufresne <nicolas@ndufresne.ca> wro=
te:
>
> Le vendredi 17 d=C3=A9cembre 2021 =C3=A0 07:15 -0600, Adam Ford a =C3=A9c=
rit :
> > On Thu, Dec 16, 2021 at 10:49 PM Ezequiel Garcia
> > <ezequiel@vanguardiasur.com.ar> wrote:
> > >
> > > Hi Adam,
> > >
> > > >
> > > > I will post a V2 last today with the Mini's post-processing removed=
.
> > > > Someone, I apologize that I forget who, mentioned it was fused out =
of
> > > > the Mini, so the testing I've been doing was with that removed and =
I
> > > > removed the H1 encoder since the Mini doesn't support JPEG encoding=
.
> > > >
> > > [...]
> > >
> > > Resurrecting this thread here. IMX8MMRM Rev. 0, 02/2019 mentions
> > > post-processor features for G1 and G2.
> > >
> > > Have you checked the fuse and synth registers to see if they throw
> > > any useful information about the hardware? For instance,
> > > comparing PP fuse register (SWREG99) and
> > > Synthesis configuration register post-processor (SWREG100)
> > > in both 8MQ and 8MM could be useful.
> > >
> > > As I mentioned on my previous mail, even if G1 PP is disabled
> > > on the Mini, I would imagine the G2 can do linear NV12 (aka raster-sc=
an)
> > > which in our hantro driver jargon is a  "post-processed" format :-)
> >
> > You're likely right.  I was going on memory from an e-mail from
> > Nicloas Defresne who wrote:
> >
> > "I will check the patchset, but you need in the mini-variant to disable=
 the G1
> > post processor, because this block was fused out. We didn't make it opt=
ional
> > from the start as according to the V1 of the TRM it was there, but that=
 error
> > was corrected in V3."
> >
> > In my head I assumed the G2 was affected as well, but when I double
> > checked his email, and based on the above statement, the G2
> > post-processing is probably there, so I'll run some tests with the G2
> > post-processing enabled.  I'll also double check those registers on
> > both to confirm what they read. I am not sure when I'll have time
> > because I leave for London next week, and I won't return until early
> > January, but I'll do what I can.
>
> Sorry if this was a bit ambiguous, indeed I meant the G1 only. I've learn=
ed
> later that the design of the Mini is that there is a good pre-processor i=
n the
> H1 block (encoder), so for the targeted use-cases this shall be sufficien=
t for
> most users (the output of the G1 is suitable for GPU and Display already,=
 so the
> post processor is not strictly needed).
>

Nicolas,

Does this mean that if the IMX8MM G2 may be able to output a wider
array of pixel formats and that the H1 encoder may be able to accept a
wider array of pixel formats? Is this code already in place in the
hantro driver and it just needs to be enabled if the IMX8MM can handle
it or is there code to be written?

I'm not clear if anyone is working on IMX8MM VPU H1 support. You had
mentioned that some support [1] and [2] can be derived from the RK3288
using the Google ChromeOS method (a v4l2 plugin that simulates in
userspace a stateful encoder). I'm not sure if this is worth pursuing
if others are working on stateless encode support in kernel and
gstreamer.

Best Regards,

Tim
[1] libv4l plugins /
https://chromium.googlesource.com/chromiumos/third_party/libv4lplugins/+/re=
fs/heads/master
[2] Kernel Driver /
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-=
4.4/drivers/media/platform/rockchip-vpu/