Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0F34C4332F for ; Fri, 17 Dec 2021 19:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240557AbhLQTLh (ORCPT ); Fri, 17 Dec 2021 14:11:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232853AbhLQTLg (ORCPT ); Fri, 17 Dec 2021 14:11:36 -0500 Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E348C061574; Fri, 17 Dec 2021 11:11:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=MIME-Version:Content-Type:References: In-Reply-To:Date:Cc:To:From:Subject:Message-ID:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=J4ub23026kjPlOzjxHivVJq/4ie0Dz90kkwgKbGyc4Q=; b=Go3CvrSCf7Eomrvxd8QnPeQ5pd dVwe61EIpJFpAIC+qHZO7DRK7lYHh9UBKV3k2t4bunC8Y36ruEQZuMBKWFqb1Edblscpka5SDRjJs CKB4l75kYxoB4B3E85rGKSQIIXIdW4sPjF4QG+eqSRYx9y1NXae33m4Yx22QKM7EiLesU5zsj8Ue/ oPOE9o2EwDU4isLTWCf5YWtGGH7l+aUSA03aAu9+m6ljQZFQ884f961WKHomzO8BLrTaQYccQMUNY UD5zWIGYIciXYPveQ6JuO+d69RWwUq1HwPPCHNcXUaMViAQiyMiC0OvJBUUsIWoF11Bkb1y4kF1Xi rI7qSegA==; Received: from [2001:8b0:10b:1::3ae] (helo=u3832b3a9db3152.infradead.org) by bombadil.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1myIdR-00C4ir-N7; Fri, 17 Dec 2021 19:11:18 +0000 Message-ID: <2bfb13ed5d565ab09bd794f69a6ef2b1b75e507a.camel@infradead.org> Subject: Re: [PATCH v3 0/9] Parallel CPU bringup for x86_64 From: David Woodhouse To: Tom Lendacky , Thomas Gleixner Cc: Ingo Molnar , Borislav Petkov , Dave Hansen , "x86@kernel.org" , "H . Peter Anvin" , Paolo Bonzini , "Paul E . McKenney" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "rcu@vger.kernel.org" , "mimoja@mimoja.de" , "hewenliang4@huawei.com" , "hushiyuan@huawei.com" , "luolongjun@huawei.com" , "hejingxian@huawei.com" Date: Fri, 17 Dec 2021 19:11:12 +0000 In-Reply-To: <1401c5a1-c8a2-cca1-e548-cab143f59d8f@amd.com> References: <20211215145633.5238-1-dwmw2@infradead.org> <761c1552-0ca0-403b-3461-8426198180d0@amd.com> <721484e0fa719e99f9b8f13e67de05033dd7cc86.camel@infradead.org> <1401c5a1-c8a2-cca1-e548-cab143f59d8f@amd.com> Content-Type: multipart/signed; micalg="sha-256"; protocol="application/pkcs7-signature"; boundary="=-OuLVbXvPdBitGtpIQfSd" User-Agent: Evolution 3.36.5-0ubuntu1 MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-OuLVbXvPdBitGtpIQfSd Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2021-12-17 at 11:48 -0600, Tom Lendacky wrote: > On 12/16/21 6:13 PM, David Woodhouse wrote: > > On Thu, 2021-12-16 at 16:52 -0600, Tom Lendacky wrote: > > > On baremetal, I haven't seen an issue. This only seems to have a prob= lem > > > with Qemu/KVM. > > >=20 > > > With 191f08997577 I could boot without issues with and without the > > > no_parallel_bringup. Only after I applied e78fa57dd642 did the failur= e happen. > > >=20 > > > With e78fa57dd642 I could boot 64 vCPUs pretty consistently, but when= I > > > jumped to 128 vCPUs it failed again. When I moved the series to > > > df9726cb7178, then 64 vCPUs also failed pretty consistently. > > >=20 > > > Strange thing is it is random. Sometimes (rarely) it works on the fir= st > > > boot and then sometimes it doesn't, at which point it will reset and > > > reboot 3 or 4 times and then make it past the failure and fully boot. > >=20 > > Hm, some of that is just artifacts of timing, I'm sure. But now I'm > > staring at the way that early_setup_idt() can run in parallel on all > > CPUs, rewriting bringup_idt_descr and loading it. > >=20 > > To start with, let's try unlocking the trampoline_lock much later, > > after cpu_init_exception_handling() has loaded the real IDT. > >=20 > > I think we can probably make secondaries load the real IDT early and > > never use bringup_idt_descr at all, can't we? But let's see if this > > makes it go away, to start with... > >=20 >=20 > This still fails. I ran with -d cpu_reset on the command line and will > forward the full log to you. I ran "grep "[ER]IP=3D" stderr.log | uniq -c= " > and got: >=20 > 128 EIP=3D00000000 EFL=3D00000000 [-------] CPL=3D0 II=3D0 A20=3D0 S= MM=3D0 HLT=3D0 > 128 EIP=3D0000fff0 EFL=3D00000002 [-------] CPL=3D0 II=3D0 A20=3D1 S= MM=3D0 HLT=3D0 > These are before running any of the vCPUs. > > 1 RIP=3Dffffffff810705c6 RFL=3D00000206 [-----P-] CPL=3D0 II=3D0 A= 20=3D1 SMM=3D0 HLT=3D0 > This is where vCPU0 is at the time of the reset. This address tends to > be different all the time and so I think it is just where it happens to > be when the reset occurs and isn't contributing to the reset. I note that one is in native_write_msr() though. I wonder what it's writing= ? Do you have console output (perhaps with earlyprintk=3DttyS0) to go with th= is? > 5 RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A= 20=3D1 SMM=3D0 HLT=3D0 > 1 RIP=3Dffffffff8104af06 RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A= 20=3D1 SMM=3D0 HLT=3D0 > 15 RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A= 20=3D1 SMM=3D0 HLT=3D0 > These are some of the APs and all are in wait_for_master_cpu(). As is right and proper. They should be coming up to that point and waiting for the... erm... controlling CPU to tell them to go any further. > 1 EIP=3D0000101b EFL=3D00000003 [------C] CPL=3D0 II=3D0 A20=3D1 S= MM=3D0 HLT=3D0 > This seems ok because: CS =3D9900 00099000 0000ffff 00009b00 > So likely in the trampoline code. Yeah, that'll be in the bitlock waiting for its turn through the real mode stack. 1010: 66 0f ba 26 18 btw $0x18,(%esi) 1015: 40 inc %eax 1016: 00 73 04 add %dh,0x4(%ebx) 1019: f3 90 pause =20 101b: eb f3 jmp 1010 > 1 EIP=3D0000fff0 EFL=3D00000002 [-------] CPL=3D0 II=3D0 A20=3D1 S= MM=3D0 HLT=3D0 > This one seems odd... could it be the one causing the reset? > CS =3Df000 ffff0000 0000ffff 00009a00 Yeah. I'm finding it slightly easier without the 'uniq'... > CPU Reset (CPU 0) > RIP=3Dffffffff810705c6 RFL=3D00000206 [-----P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 1) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 2) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 3) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 4) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 5) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 6) > RIP=3Dffffffff8104af06 RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 7) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 8) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 9) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 10) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 11) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 12) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 13) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 14) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 15) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 16) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 17) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 18) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 19) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 20) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 21) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 All those came up and are waiting in wait_for_master_cpu() as they should. > CPU Reset (CPU 22) > EIP=3D0000101b EFL=3D00000003 [------C] CPL=3D0 II=3D0 A20=3D1 SMM=3D0 HL= T=3D0 That one's in the bitlock, also waiting. > CPU Reset (CPU 23) > EIP=3D0000fff0 EFL=3D00000002 [-------] CPL=3D0 II=3D0 A20=3D1 SMM=3D0 HL= T=3D0 This one we suspect. Is this what a triple-fault would look like? Not if it's *already* at f000:fff0, surely?=20 CPU Reset (CPU 23) EAX=3D00000000 EBX=3D00000000 ECX=3D00000000 EDX=3D00800f12 ESI=3D00000000 EDI=3D00000000 EBP=3D00000000 ESP=3D00000000 EIP=3D0000fff0 EFL=3D00000002 [-------] CPL=3D0 II=3D0 A20=3D1 SMM=3D0 HLT= =3D0 ES =3D0000 00000000 0000ffff 00009300 CS =3Df000 ffff0000 0000ffff 00009a00 SS =3D0000 00000000 0000ffff 00009200 DS =3D0000 00000000 0000ffff 00009300 FS =3D0000 00000000 0000ffff 00009300 GS =3D0000 00000000 0000ffff 00009300 LDT=3D0000 00000000 0000ffff 00008200 TR =3D0000 00000000 0000ffff 00008300 GDT=3D 00000000 0000ffff IDT=3D 00000000 0000ffff CR0=3D00000010 CR2=3D00000000 CR3=3D00000000 CR4=3D00000000 DR0=3D0000000000000000 DR1=3D0000000000000000 DR2=3D0000000000000000 DR3=3D= 0000000000000000=20 DR6=3D00000000ffff0ff0 DR7=3D0000000000000400 CCS=3D00000000 CCD=3D00000000 CCO=3DDYNAMIC=20 EFER=3D0000000000000000 FCW=3D037f FSW=3D0000 [ST=3D0] FTW=3D00 MXCSR=3D00001f80 FPR0=3D0000000000000000 0000 FPR1=3D0000000000000000 0000 FPR2=3D0000000000000000 0000 FPR3=3D0000000000000000 0000 FPR4=3D0000000000000000 0000 FPR5=3D0000000000000000 0000 FPR6=3D0000000000000000 0000 FPR7=3D0000000000000000 0000 XMM00=3D0000000000000000 0000000000000000 XMM01=3D0000000000000000 00000000= 00000000 XMM02=3D0000000000000000 0000000000000000 XMM03=3D0000000000000000 00000000= 00000000 XMM04=3D0000000000000000 0000000000000000 XMM05=3D0000000000000000 00000000= 00000000 XMM06=3D0000000000000000 0000000000000000 XMM07=3D0000000000000000 00000000= 00000000 > CPU Reset (CPU 24) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 25) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 > CPU Reset (CPU 26) > RIP=3Dffffffff8104aefb RFL=3D00000046 [---Z-P-] CPL=3D0 II=3D0 A20=3D1 SM= M=3D0 HLT=3D0 These ones made it through the real mode first and are also waiting. > CPU Reset (CPU 27) > EIP=3D0000101b EFL=3D00000003 [------C] CPL=3D0 II=3D0 A20=3D1 SMM=3D0 HL= T=3D0 > CPU Reset (CPU 28) > EIP=3D0000101b EFL=3D00000003 [------C] CPL=3D0 II=3D0 A20=3D1 SMM=3D0 HL= T=3D0 > CPU Reset (CPU 29) Still in the real mode bitlock. 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