Message-ID: <1e68760ba5452ec23f89485b20f8aa3bf9f9b039.camel@infradead.org>
Subject: Re: [PATCH v3 0/9] Parallel CPU bringup for x86_64
From:   David Woodhouse <dwmw2@infradead.org>
To:     Tom Lendacky <thomas.lendacky@amd.com>,
        Thomas Gleixner <tglx@linutronix.de>
Cc:     Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        "x86@kernel.org" <x86@kernel.org>,
        "H . Peter Anvin" <hpa@zytor.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        "Paul E . McKenney" <paulmck@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
        "rcu@vger.kernel.org" <rcu@vger.kernel.org>,
        "mimoja@mimoja.de" <mimoja@mimoja.de>,
        "hewenliang4@huawei.com" <hewenliang4@huawei.com>,
        "hushiyuan@huawei.com" <hushiyuan@huawei.com>,
        "luolongjun@huawei.com" <luolongjun@huawei.com>,
        "hejingxian@huawei.com" <hejingxian@huawei.com>
Date:   Fri, 17 Dec 2021 22:48:12 +0000
In-Reply-To: <c3dbd3b9-accf-bc28-f808-1d842d642309@amd.com>
References: <20211215145633.5238-1-dwmw2@infradead.org>
         <761c1552-0ca0-403b-3461-8426198180d0@amd.com>
         <ca0751c864570015ffe4d8cccdc94e0a5ef3086d.camel@infradead.org>
         <b13eac6c-ea87-aef9-437f-7266be2e2031@amd.com>
         <721484e0fa719e99f9b8f13e67de05033dd7cc86.camel@infradead.org>
         <1401c5a1-c8a2-cca1-e548-cab143f59d8f@amd.com>
         <2bfb13ed5d565ab09bd794f69a6ef2b1b75e507a.camel@infradead.org>
         <b798bcef-d750-ce42-986c-0d11d0bb47b0@amd.com>
         <41e63d89f1b2debc0280f243d7c8c3212e9499ee.camel@infradead.org>
         <c3dbd3b9-accf-bc28-f808-1d842d642309@amd.com>
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On Fri, 2021-12-17 at 14:55 -0600, Tom Lendacky wrote:
> On 12/17/21 2:13 PM, David Woodhouse wrote:
> > On Fri, 2021-12-17 at 13:46 -0600, Tom Lendacky wrote:
> > > There's no WARN or PANIC, just a reset. I can look to try and capture=
 some
> > > KVM trace data if that would help. If so, let me know what events you=
'd
> > > like captured.
> >=20
> >=20
> > Could start with just kvm_run_exit?
> >=20
> > Reason 8 would be KVM_EXIT_SHUTDOWN and would potentially indicate a
> > triple fault.
>=20
> qemu-system-x86-24093   [005] .....  1601.759486: kvm_exit: vcpu 112 reas=
on shutdown rip 0xffffffff81070574 info1 0x0000000000000000 info2 0x0000000=
000000000 intr_info 0x80000b08 error_code 0x00000000
>=20
> # addr2line -e woodhouse-build-x86_64/vmlinux 0xffffffff81070574
> /root/kernels/woodhouse-build-x86_64/./arch/x86/include/asm/desc.h:272
>=20
> Which is: asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));

OK, that seems like enough of a smoking gun; I'll stare at that harder. Tha=
nks.

/*
 * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT =
is
 * a read-only remapping. To prevent a page fault, the GDT is switched to t=
he
 * original writeable version when needed.
 */
#ifdef CONFIG_X86_64
static inline void native_load_tr_desc(void)
{
        struct desc_ptr gdt;
        int cpu =3D raw_smp_processor_id();
        bool restore =3D 0;
        struct desc_struct *fixmap_gdt;

        native_store_gdt(&gdt);
        fixmap_gdt =3D get_cpu_gdt_ro(cpu);

        /*
         * If the current GDT is the read-only fixmap, swap to the original
         * writeable version. Swap back at the end.
         */
        if (gdt.address =3D=3D (unsigned long)fixmap_gdt) {
                load_direct_gdt(cpu);
                restore =3D 1;
        }
        asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
        if (restore)
                load_fixmap_gdt(cpu);
}

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