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References: <20211220072332.81072-1-reinhold.mueller@emtrion.com> <20211220072332.81072-3-reinhold.mueller@emtrion.com>
In-Reply-To: <20211220072332.81072-3-reinhold.mueller@emtrion.com>
From:   Fabio Estevam <festevam@gmail.com>
Date:   Mon, 20 Dec 2021 21:06:25 -0300
Message-ID: <CAOMZO5BvLZYh3=q_-XNcw-v5wDcBpR3Qo26Gd3hTtJ_a-FQiuA@mail.gmail.com>
Subject: Re: [PATCH v4 2/2] arm64: dts: imx8mm: Add support for emtrion
 emCON-MX8M Mini
To:     reinhold.mueller@emtrion.com
Cc:     Rob Herring <robh+dt@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Sascha Hauer <kernel@pengutronix.de>,
        Shawn Guo <shawnguo@kernel.org>,
        NXP Linux Team <linux-imx@nxp.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>
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Precedence: bulk

Hi Reinhold,

On Mon, Dec 20, 2021 at 4:23 AM <reinhold.mueller@emtrion.com> wrote:

> +       pinctrl_ecspi1: ecspi1-grp {
> +               fsl,pins = <
> +                       MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK            0x82
> +                       MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI            0x82
> +                       MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO            0x82
> +               >;
> +       };
> +
> +       pinctrl_ecspi1_cs: ecspi1-cs {
> +               fsl,pins = <
> +                       MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x40000
> +                       MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x40000

This version looks good to me.

One nit: you seem to use a single SPI chipselect, but you add two entries here.

Is the MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 needed too?

Either way:

Reviewed-by: Fabio Estevam <festevam@gmail.com>