Subject: Re: [PATCH v2 1/3] ALSA: hda/tegra: Fix Tegra194 HDA reset failure
To:     Dmitry Osipenko <digetx@gmail.com>, tiwai@suse.com,
        broonie@kernel.org, lgirdwood@gmail.com, robh+dt@kernel.org,
        thierry.reding@gmail.com, perex@perex.cz
Cc:     jonathanh@nvidia.com, mkumard@nvidia.com,
        alsa-devel@alsa-project.org, devicetree@vger.kernel.org,
        linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
        stable@vger.kernel.org
References: <1640021408-12824-1-git-send-email-spujar@nvidia.com>
 <1640021408-12824-2-git-send-email-spujar@nvidia.com>
 <f859559c-abf1-ae37-6a0f-80329e6f747f@gmail.com>
From:   Sameer Pujar <spujar@nvidia.com>
Message-ID: <f65ae56d-d289-9e3f-1c15-f0bedda3918c@nvidia.com>
Date:   Tue, 21 Dec 2021 11:48:57 +0530
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 =?utf-8?B?aExUSFFVNVppNFY2OFQ2MWVRSkJHdDQzZERkeUZqY3lhVHRUNFFwZ2JESmQ5?=
 =?utf-8?B?eVUzZTFjbE85RGFxSEFYdDBINUlJWGFlWXFFSmhTLzR2N0FVNEk5UzViQ1Q0?=
 =?utf-8?B?c1RVYjJ5M1ZHM1dLVEZSazR4TzVyTnRWdGd5QWxUZmZjTXNIcXJDcU93MXQ1?=
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 =?utf-8?B?ekZCM05xczdQZWplanY0OGZTTXpTU3JLRzZRbG03eWFzUWVpK0NYZmU1c1o1?=
 =?utf-8?B?SXBlemRrOFY1RURJamdpUndsc3laajN3Z05RalFzakV4UmU2eVFnUXl2SjVZ?=
 =?utf-8?B?VFFCR01kd2N4Y2tGajRUTmxuemdJSFcwVVdVUXNabnB3NGpYOUVLY2dwQmdJ?=
 =?utf-8?B?a2xCdktPK2dlaExYdXZNNGs1Ym9tRXlpWjBGM0dlbEJrajhnbkZrNmhVUVVB?=
 =?utf-8?B?ZTBHZ3dXWk1keWg3RExjOFYydTZieDJhbmtJeDNDaGVwalJGSnNVWEhvWEFQ?=
 =?utf-8?B?d1BFZ2RzenBXc0ttUFdQWTJUd0F6eUYvQXJqME5vYmpMS1VscCtxTUVNa0d3?=
 =?utf-8?B?eXlwc0N1OTd0bk5nWWtCRTlCcXQxcDVvcE1uN2VKcXVQUlI3NmxZVFVUUlRS?=
 =?utf-8?B?Y2JiM09zc1hBSHdTQ0d0VjdaSFNJdXpHUzh2TlpKeEYzbzdoQjV1bkVFTDE3?=
 =?utf-8?B?ODZXYVJqRUJTRGV2ZmE0akw1NHkrYUdLenJQUjV0VEUzQ2VOSm1yWHliTDVU?=
 =?utf-8?B?WHk4N1VHeit4c01DdXRPb3pOdDFLbEFwUkpNVE9BOFRoOVVTZDNXSVlwQ1JY?=
 =?utf-8?B?ajVZUVhhdGExRDRKcnNHODEzRVp2NGNHWUlDOXhYcno4UHJHL2pnYm9tVlhn?=
 =?utf-8?B?N051U0R2bUN2SERpekJqaFpGNXIwVElrenRqcStTL1Z3eCtsa3g4M0NiVE9i?=
 =?utf-8?B?WVJJN1hxQk4zL3lONThYcC9INjdyOWNLV3hvMEJtQXdReFdqTFRBcDU3eWV2?=
 =?utf-8?B?TlY5ZGVTZStWL3p3dlprWW5RWit3ZlZHUTIwV1dFS0tMV1dGaTk0ZmZIWXp3?=
 =?utf-8?B?UFByYk52NFRTamNTWE9sUVhra3VtNXkrRnN0cmpjS1dnSjdRazA5Z0l5QmZI?=
 =?utf-8?B?bUxUdnBCWlNJdmJ5OUhsNHcwSmJQblM3VGZrL04rcDMxQ0FpdFJqOGovNGVx?=
 =?utf-8?B?SWRvWGo3dFg1NGtZOVlZZW44clI5Zm5uT3hhcVFXL3VrbkZ2RTBJWm5NUHVq?=
 =?utf-8?B?cmZSamJFZFptbEF4SGZkRjdDKzV2V2R5TUJmQjhHanV5YnpDRzZqYzBDMFVv?=
 =?utf-8?B?QTY1RitwajVWb3dyL2Nab3V0MHBTMEc2UTVLc1gyUlFPR2tXREJYb2VUb3BD?=
 =?utf-8?B?anNWT0x4VVcxR3lCQjh5RkVUWmVReEVZV3lJbGxQbmJ3aGhJeHMvdGRMbzYy?=
 =?utf-8?B?aTlGeWc1MGRGYnNDdENZNDhHZlMxM1JZbXNLUllOMW0vL3RRclJBM1doVlk0?=
 =?utf-8?B?RUVGQ0tGZnJLWEdXcEZUSTdzTWYwVlI0WEVGN0lyb2dTaW9wLzErSHBUcldx?=
 =?utf-8?B?RzVGNmNJUHVjT0ZNUGE1MnRZOWtERE50YWNZekhrSWF0SnRySGlmY1ZQZzJY?=
 =?utf-8?B?YVNWSEJ2cC9ONk5uOElZZDV5WDJJdUlTeVVCdEZVWGJiTDJDeDhBRElRV1Ar?=
 =?utf-8?B?WXNna1VlTVpxVy8rUUlUMXJxUEhRK29vcVh3cGFBTytFNDc4VUlDaTY5aUdJ?=
 =?utf-8?Q?UhkDqdTZLEz/OINtx7wvO2A=3D?=
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On 12/21/2021 6:51 AM, Dmitry Osipenko wrote:
>
> All stable kernels affected by this problem that don't support the bulk
> reset API are EOL now. Please use bulk reset API like I suggested in the
> comment to v1, it will allow us to have a cleaner and nicer code.

Agree that it would be compact and cleaner, but any specific reset 
failure in the group won't be obvious in the logs. In this case it 
failed silently. If compactness is preferred, then may be I can keep an 
error print at group level so that we see some failure context whenever 
it happens.