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Subject: Re: [PATCH v1 2/2] dt-bindings: riscv: Add DT binding for RISC-V ISA
 extensions
From:   Jessica Clarke <jrtc27@jrtc27.com>
In-Reply-To: <20211224211632.1698523-3-atishp@rivosinc.com>
Date:   Fri, 24 Dec 2021 23:25:01 +0000
Cc:     linux-kernel@vger.kernel.org, Atish Patra <atishp@rivosinc.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Anup Patel <anup@brainfault.org>,
        Damien Le Moal <damien.lemoal@wdc.com>,
        devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
        linux-riscv@lists.infradead.org,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Rob Herring <robh+dt@kernel.org>
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References: <20211224211632.1698523-1-atishp@rivosinc.com>
 <20211224211632.1698523-3-atishp@rivosinc.com>
To:     Atish Patra <atishp@atishpatra.org>
Precedence: bulk

On 24 Dec 2021, at 21:16, Atish Patra <atishp@atishpatra.org> wrote:
>=20
> RISC-V ISA extensions can be single letter or multi-letter names.
> The single letter extensions are mostly base extensions and encoded in
> "riscv,isa" DT property. However, parsing the multi-letter extensions
> via the isa string is cumbersome and is not scalable.
>=20
> Add a new DT node for multi-letter extensions.
>=20
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml =
b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index aa5fb64d57eb..6c4eecf389a9 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -78,6 +78,15 @@ properties:
>       - rv64imac
>       - rv64imafdc
>=20
> +  riscv,isa-ext:
> +    description:
> +      Identifies the specific RISC-V instruction set architecture =
extensions
> +      supported by one or multiple harts. All the multi-letter =
extensions
> +      should be listed here as a boolean property. This subnode can =
be under
> +      /cpus or under individual cpu node. In case of former, it =
represent
> +      the common ISA extensions for all harts. The name of the =
boolean property
> +      must match the actual ISA extension name in all lowercase =
format.

I don=E2=80=99t see why this needs explicitly calling out, that=E2=80=99s =
true in
general of cpu node properties (3.8p4 of the Devicetree spec v0.4-rc1 /
v0.3-40-g7e1cc17), not that I like it.

Jess