Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D664C433FE for ; Mon, 27 Dec 2021 20:04:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232654AbhL0UE2 (ORCPT ); Mon, 27 Dec 2021 15:04:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230053AbhL0UE0 (ORCPT ); Mon, 27 Dec 2021 15:04:26 -0500 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6ADBC06173E; Mon, 27 Dec 2021 12:04:25 -0800 (PST) Received: by mail-ed1-x536.google.com with SMTP id w16so65541831edc.11; Mon, 27 Dec 2021 12:04:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=P8q6ExHPHeCoatQ2Or3qWHD1pWM6+APCs/H8EAPVzyY=; b=PO260IgRHd9vbc20rDBveu9gAeHOr0WaB2czdvNwspZ3Kp9pmODWH+WIcSjWwdL2/q vDQBpAPlBpQVd2G8Q5/LGWk3RqND028G4iTkthcyt4TGaoYCXsEKR8LdKY4qJlnMqbyl 6yvCzHw09LREYZhhxM+U1MnaYj0S8ILJf8BPLzLSzih7bzGA8IiYXgRGaFK1blxhHHR9 JhjvqJtnGDPGhxTS7m/FyHLYiQFKbNnuB3yVquaFJuzcPyrBkfgN2EhObFJ5kUK7FQq/ 3Sh26fu69ISq9SCtE0zNw/WpaI7IVHsRaiBRW6omlOFQU8HIR5ke6ByqB4v1PzUai+59 ahZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=P8q6ExHPHeCoatQ2Or3qWHD1pWM6+APCs/H8EAPVzyY=; b=PChFRupO5kM563lPjfkdUlFdRCR/L9f/cp17T9IdNVZZ9wLf+YdqJEQIwOyD7BYcIy JO9xl3P7XJaoYN7221yMABZBBD1dLuxdL+nQMd7imZFUTVqXo3AEfw0Po7bqmMjxvADL 6Mh4ZkcPdNzcttCnv/u7cs2JpuHFoCPAlE/Tw83VnN7350Gh6XLpIc/HJnjZUVROMeRX JAXWYtok9v25K902O/LC5DT+OFASk2V4gWMsKPIWCH15g+HadvtEf/QDyfE0OjY4aTAJ AQKxYO4y3iQqqMwMl2o68RDFZFC6eKzaeJQzOrlUSbRSQhdHbODnU1vPSDHjQrD+YbR+ qQQQ== X-Gm-Message-State: AOAM532JQq/70KaHRSRoiC27zGk2INVGsUMTwV/AkXPZxYM0sSgIwHLL r+9nHefkZQZX3/tB6H0Jmsbav5QhAw8JwKyHSQ7cixVJvTA= X-Google-Smtp-Source: ABdhPJzxzwd3Jhu/Sm2Vh5AXMvFTI+1L7i/CnGGve5tvPMyJA49y+PpooJoz1qyw0+eD4O3IEX30qAyrZXoorjpFj6U= X-Received: by 2002:a05:6402:518a:: with SMTP id q10mr15268102edd.29.1640635464371; Mon, 27 Dec 2021 12:04:24 -0800 (PST) MIME-Version: 1.0 References: <20211221071634.25980-1-yu.tu@amlogic.com> <20211221071634.25980-4-yu.tu@amlogic.com> In-Reply-To: From: Martin Blumenstingl Date: Mon, 27 Dec 2021 21:04:13 +0100 Message-ID: Subject: Re: [PATCH 3/3] tty: serial: meson: add UART driver compatible with S4 SoC on-chip To: Yu Tu Cc: linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , Jiri Slaby , Neil Armstrong , Kevin Hilman , Jerome Brunet Content-Type: multipart/mixed; boundary="0000000000000f725305d42636f6" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --0000000000000f725305d42636f6 Content-Type: text/plain; charset="UTF-8" Hello, On Mon, Dec 27, 2021 at 7:56 AM Yu Tu wrote: [...] > > Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL? > > If there's still a 24MHz XTAL then I think this description is not > > correct - at least based on how I understand the UART controller. > > > The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in romcode). > This register description is the same as the G12A and G12B you know. Thank you for this explanation! So the problem is that we're not touching bit 26 and bit 27 - and with the updated romcode you would not get any serial output since the divider is calculated off the wrong clock. I agree with Jerome that we shouldn't put a flag in device-tree. Also I did some experimenting with Jerome's idea to implement the clocks using CCF (common clock framework), see the attached patches. It was a bit tricky because some initial clean-ups were needed in the serial driver. Note: I have only briefly tested this on a 32-bit Meson8m2 SoC, see my attached patches and the clk_summary debugfs output. In fact, I expect that there are some issues with at least one of the patches as the whole bit 26 and bit 27 code is untested. Do you see any problems with this patch? Could you try to implement CCF support with the idea from the attached patches (you don't need to re-use them, I just wrote them to make it clearer in our discussion what we're talking about). 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