Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80BD6C433FE for ; Tue, 28 Dec 2021 14:19:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233504AbhL1OTb (ORCPT ); Tue, 28 Dec 2021 09:19:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233392AbhL1OT2 (ORCPT ); Tue, 28 Dec 2021 09:19:28 -0500 Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69057C061574; Tue, 28 Dec 2021 06:19:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=MIME-Version:Content-Type:References: In-Reply-To:Date:Cc:To:From:Subject:Message-ID:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=zjMrvgbvV5nTf1FdevmTVKswuEAf8gsVzE1dnD13VnQ=; b=REzsEZI6dxHdLlM6Vz1Ac5uNGO qxVNv0eR3Cu03BDlzmFxJqcmg0/GDBmKGsa9GCOoTAs/RhZYW1CSEqfJgIdiH98x0JHWcFaX6Pp8b O6/pENQr9KOWBBVj0Yu2gdDdc960pKir0jlmTciqC7qsJOfiE8lDNMm+GTkFjiFFIvK7Y9HExGvjB PAi+7o9xma7XcPd3W/qXZgIS7cKvLX38r483QFqqTRq2hwSFtaPpYIVvAsLit2wa1RzYuJCgHHaLh 4VDdgmDJ65O0Y/TQVXCIoiDVoijO0tyLlQWSylDzswHm4Ihs26UcnGjxEHEcOlDXleGUVjjrScw6e tBsuZaag==; Received: from [2001:8b0:10b:1::3ae] (helo=u3832b3a9db3152.ant.amazon.com) by bombadil.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1n2DJd-0016V8-Qs; Tue, 28 Dec 2021 14:19:02 +0000 Message-ID: <3bfacf45d2d0f3dfa3789ff5a2dcb46744aacff7.camel@infradead.org> Subject: Re: [PATCH v3 0/9] Parallel CPU bringup for x86_64 From: David Woodhouse To: Paul Menzel , Thomas Gleixner Cc: Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Paolo Bonzini , "Paul E . McKenney" , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, rcu@vger.kernel.org, mimoja@mimoja.de, hewenliang4@huawei.com, hushiyuan@huawei.com, luolongjun@huawei.com, hejingxian@huawei.com Date: Tue, 28 Dec 2021 14:18:57 +0000 In-Reply-To: References: <20211215145633.5238-1-dwmw2@infradead.org> <9a47b5ec-f2d1-94d9-3a48-9b326c88cfcb@molgen.mpg.de> Content-Type: multipart/signed; micalg="sha-256"; protocol="application/pkcs7-signature"; boundary="=-KgIakeObTsASOH4+JQVM" User-Agent: Evolution 3.36.5-0ubuntu1 MIME-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org. See http://www.infradead.org/rpr.html Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-KgIakeObTsASOH4+JQVM Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2021-12-28 at 12:34 +0100, Paul Menzel wrote: > Same on the ASUS F2A85-M PRO with AMD A6-6400K. Without serial console,= =20 > the messages below are printed below to the monitor after nine seconds. >=20 > [ 1.078879] smp: Bringing up secondary CPUs ... > [ 1.080950] x86: Booting SMP configuration: >=20 > Please find the serial log attached. >=20 Thanks for testing. That looks like the same triple-fault on bringup that we have been seeing, and that I reproduced without my patches using kexec all the way back to a 5.0 kernel. Out of interest, are you also able to reproduce it with kexec and without the parallel bringup? And with that patch I sent Tom in =20 https://lore.kernel.org/lkml/721484e0fa719e99f9b8f13e67de05033dd7cc86.camel= @infradead.org/ to expand the bitlock exclusion and stop the bringup being truly in parallel at all? Or tbe one in https://lore.kernel.org/lkml/d4cde50b4aab24612823714dfcbe69bc4bb63b60.camel= @infradead.org which makes it do nothing except prepare all the CPUs before bringing them up one at a time? My current theory (not that I've spent that much time thinking about it in the last week) is that there's something about the existing CPU bringup, possibly a CPU bug or something special about the AMD CPUs, which is triggered by just making it a little bit *faster*, which is why bringing them up from kexec (especially in qemu) can cause it too? Tom seemed to find that it was in load_TR_desc(), so if you could try this hack on a machine that doesn't magically wink out of existence on a triplefault before even flushing its serial output, that would be much appreciated... diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h index ab97b22ac04a..cc6590712ff4 100644 --- a/arch/x86/include/asm/desc.h +++ b/arch/x86/include/asm/desc.h @@ -8,7 +8,7 @@ #include #include #include - +#include #include #include #include @@ -265,11 +265,16 @@ static inline void native_load_tr_desc(void) * If the current GDT is the read-only fixmap, swap to the original * writeable version. Swap back at the end. */ + outb('d', 0x3f8); if (gdt.address =3D=3D (unsigned long)fixmap_gdt) { + outb('e', 0x3f8); load_direct_gdt(cpu); restore =3D 1; + outb('f', 0x3f8); } + outb('g', 0x3f8); asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); + outb('h', 0x3f8); if (restore) load_fixmap_gdt(cpu); } diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 0083464de5e3..5bc8f30c3283 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1716,7 +1716,9 @@ void identify_secondary_cpu(struct cpuinfo_x86 *c) enable_sep_cpu(); #endif mtrr_ap_init(); +outb('A', 0x3f8); validate_apic_and_package_id(c); +outb('B', 0x3f8); x86_spec_ctrl_setup_ap(); update_srbds_msr(); } @@ -1957,6 +1959,7 @@ static inline void tss_setup_io_bitmap(struct tss_str= uct *tss) tss->io_bitmap.mapall[IO_BITMAP_LONGS] =3D ~0UL; #endif } +#include =20 /* * Setup everything needed to handle exceptions from the IDT, including th= e IST @@ -1969,16 +1972,24 @@ void cpu_init_exception_handling(void) =20 /* paranoid_entry() gets the CPU number from the GDT */ setup_getcpu(cpu); - + outb('\n', 0x3f8); + outb('0' + cpu / 100, 0x3f8); + outb('0' + (cpu % 100) / 10, 0x3f8); + outb('0' + (cpu % 10), 0x3f8); +=09 /* IST vectors need TSS to be set up. */ tss_setup_ist(tss); + outb('a', 0x3f8); tss_setup_io_bitmap(tss); set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); - + outb('b', 0x3f8); load_TR_desc(); + outb('c', 0x3f8); =20 /* Finally load the IDT */ load_current_idt(); + outb('z', 0x3f8); + } =20 /* --=-KgIakeObTsASOH4+JQVM Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCCECow ggUcMIIEBKADAgECAhEA4rtJSHkq7AnpxKUY8ZlYZjANBgkqhkiG9w0BAQsFADCBlzELMAkGA1UE BhMCR0IxGzAZBgNVBAgTEkdyZWF0ZXIgTWFuY2hlc3RlcjEQMA4GA1UEBxMHU2FsZm9yZDEaMBgG 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