Date:   Wed, 29 Dec 2021 16:35:48 +0900
From:   William Breathitt Gray <vilhelm.gray@gmail.com>
To:     Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
Cc:     Lars-Peter Clausen <lars@metafoo.de>, kernel@pengutronix.de,
        Jonathan Cameron <Jonathan.Cameron@huawei.com>,
        linux-iio@vger.kernel.org,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        linux-kernel@vger.kernel.org,
        Jarkko Nikula <jarkko.nikula@linux.intel.com>,
        "Felipe Balbi (Intel)" <balbi@kernel.org>,
        Raymond Tan <raymond.tan@intel.com>
Subject: Re: [PATCH v2 08/23] counter: intel-qep: Convert to counter_priv()
 wrapper
Message-ID: <YcwP1JeLETPd6dqK@shinobu>
References: <20211227094526.698714-1-u.kleine-koenig@pengutronix.de>
 <20211227094526.698714-9-u.kleine-koenig@pengutronix.de>
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On Mon, Dec 27, 2021 at 10:45:11AM +0100, Uwe Kleine-K=C3=B6nig wrote:
> This is a straight forward conversion to the new counter_priv() wrapper.
>=20
> Signed-off-by: Uwe Kleine-K=C3=B6nig <u.kleine-koenig@pengutronix.de>

Acked-by: William Breathitt Gray <vilhelm.gray@gmail.com>

> ---
>  drivers/counter/intel-qep.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
>=20
> diff --git a/drivers/counter/intel-qep.c b/drivers/counter/intel-qep.c
> index 0924d16de6e2..8f84a48508ac 100644
> --- a/drivers/counter/intel-qep.c
> +++ b/drivers/counter/intel-qep.c
> @@ -109,7 +109,7 @@ static void intel_qep_init(struct intel_qep *qep)
>  static int intel_qep_count_read(struct counter_device *counter,
>  				struct counter_count *count, u64 *val)
>  {
> -	struct intel_qep *const qep =3D counter->priv;
> +	struct intel_qep *const qep =3D counter_priv(counter);
> =20
>  	pm_runtime_get_sync(qep->dev);
>  	*val =3D intel_qep_readl(qep, INTEL_QEPCOUNT);
> @@ -176,7 +176,7 @@ static struct counter_synapse intel_qep_count_synapse=
s[] =3D {
>  static int intel_qep_ceiling_read(struct counter_device *counter,
>  				  struct counter_count *count, u64 *ceiling)
>  {
> -	struct intel_qep *qep =3D counter->priv;
> +	struct intel_qep *qep =3D counter_priv(counter);
> =20
>  	pm_runtime_get_sync(qep->dev);
>  	*ceiling =3D intel_qep_readl(qep, INTEL_QEPMAX);
> @@ -188,7 +188,7 @@ static int intel_qep_ceiling_read(struct counter_devi=
ce *counter,
>  static int intel_qep_ceiling_write(struct counter_device *counter,
>  				   struct counter_count *count, u64 max)
>  {
> -	struct intel_qep *qep =3D counter->priv;
> +	struct intel_qep *qep =3D counter_priv(counter);
>  	int ret =3D 0;
> =20
>  	/* Intel QEP ceiling configuration only supports 32-bit values */
> @@ -213,7 +213,7 @@ static int intel_qep_ceiling_write(struct counter_dev=
ice *counter,
>  static int intel_qep_enable_read(struct counter_device *counter,
>  				 struct counter_count *count, u8 *enable)
>  {
> -	struct intel_qep *qep =3D counter->priv;
> +	struct intel_qep *qep =3D counter_priv(counter);
> =20
>  	*enable =3D qep->enabled;
> =20
> @@ -223,7 +223,7 @@ static int intel_qep_enable_read(struct counter_devic=
e *counter,
>  static int intel_qep_enable_write(struct counter_device *counter,
>  				  struct counter_count *count, u8 val)
>  {
> -	struct intel_qep *qep =3D counter->priv;
> +	struct intel_qep *qep =3D counter_priv(counter);
>  	u32 reg;
>  	bool changed;
> =20
> @@ -256,7 +256,7 @@ static int intel_qep_spike_filter_ns_read(struct coun=
ter_device *counter,
>  					  struct counter_count *count,
>  					  u64 *length)
>  {
> -	struct intel_qep *qep =3D counter->priv;
> +	struct intel_qep *qep =3D counter_priv(counter);
>  	u32 reg;
> =20
>  	pm_runtime_get_sync(qep->dev);
> @@ -277,7 +277,7 @@ static int intel_qep_spike_filter_ns_write(struct cou=
nter_device *counter,
>  					   struct counter_count *count,
>  					   u64 length)
>  {
> -	struct intel_qep *qep =3D counter->priv;
> +	struct intel_qep *qep =3D counter_priv(counter);
>  	u32 reg;
>  	bool enable;
>  	int ret =3D 0;
> @@ -326,7 +326,7 @@ static int intel_qep_preset_enable_read(struct counte=
r_device *counter,
>  					struct counter_count *count,
>  					u8 *preset_enable)
>  {
> -	struct intel_qep *qep =3D counter->priv;
> +	struct intel_qep *qep =3D counter_priv(counter);
>  	u32 reg;
> =20
>  	pm_runtime_get_sync(qep->dev);
> @@ -341,7 +341,7 @@ static int intel_qep_preset_enable_read(struct counte=
r_device *counter,
>  static int intel_qep_preset_enable_write(struct counter_device *counter,
>  					 struct counter_count *count, u8 val)
>  {
> -	struct intel_qep *qep =3D counter->priv;
> +	struct intel_qep *qep =3D counter_priv(counter);
>  	u32 reg;
>  	int ret =3D 0;
> =20
> --=20
> 2.33.0
>=20

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