Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3246C433FE for ; Thu, 30 Dec 2021 08:48:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238047AbhL3Isp (ORCPT ); Thu, 30 Dec 2021 03:48:45 -0500 Received: from lucky1.263xmail.com ([211.157.147.131]:32968 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237879AbhL3Isi (ORCPT ); Thu, 30 Dec 2021 03:48:38 -0500 Received: from localhost (unknown [192.168.167.16]) by lucky1.263xmail.com (Postfix) with ESMTP id 01EF5CAF8D; Thu, 30 Dec 2021 16:48:36 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P12624T140277015766784S1640854098676227_; Thu, 30 Dec 2021 16:48:35 +0800 (CST) X-IP-DOMAINF: 1 X-RL-SENDER: yifeng.zhao@rock-chips.com X-SENDER: zyf@rock-chips.com X-LOGIN-NAME: yifeng.zhao@rock-chips.com X-FST-TO: heiko@sntech.de X-RCPT-COUNT: 17 X-LOCAL-RCPT-COUNT: 4 X-MUTI-DOMAIN-COUNT: 0 X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-UNIQUE-TAG: <69123dd2a47d8723f9ae95b2732f3e01> X-System-Flag: 0 From: Yifeng Zhao To: heiko@sntech.de Cc: robh+dt@kernel.org, jbx6244@gmail.com, devicetree@vger.kernel.org, vkoul@kernel.org, michael.riesch@wolfvision.net, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, kishon@ti.com, p.zabel@pengutronix.de, cl@rock-chips.com, kever.yang@rock-chips.com, lee.jones@linaro.org, wulf@rock-chips.com, Yifeng Zhao Subject: [PATCH v7 4/4] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 Date: Thu, 30 Dec 2021 16:48:15 +0800 Message-Id: <20211230084815.28110-5-yifeng.zhao@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211230084815.28110-1-yifeng.zhao@rock-chips.com> References: <20211230084815.28110-1-yifeng.zhao@rock-chips.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the core dt-node for the rk3568's naneng combo phys. Signed-off-by: Yifeng Zhao Signed-off-by: Johan Jonker --- Changes in v7: None Changes in v5: - remove apb reset Changes in v4: - rename node name - remove reset-names - move #phy-cells - add rockchip,rk3568-pipe-grf - add rockchip,rk3568-pipe-phy-grf Changes in v3: - Move pipe_phy_grf0 to rk3568.dtsi Changes in v2: - Move phy0 to rk3568.dtsi arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 2fd313a295f8..91a0b798b857 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,11 @@ / { compatible = "rockchip,rk3568"; + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + qos_pcie3x1: qos@fe190080 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe190080 0x0 0x20>; @@ -71,6 +76,22 @@ queue0 {}; }; }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + status = "disabled"; + }; }; &cpu0_opp_table { diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index a68033a23975..93f230f799f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -218,11 +218,26 @@ }; }; + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + grf: syscon@fdc60000 { compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; reg = <0x0 0xfdc60000 0x0 0x10000>; }; + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; @@ -1141,6 +1156,38 @@ status = "disabled"; }; + combphy1: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, + <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; + status = "disabled"; + }; + + combphy2: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, + <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>; -- 2.17.1