Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C5A1C433F5 for ; Thu, 30 Dec 2021 09:36:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238336AbhL3Jg2 (ORCPT ); Thu, 30 Dec 2021 04:36:28 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:52878 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234584AbhL3Jg1 (ORCPT ); Thu, 30 Dec 2021 04:36:27 -0500 X-UUID: a8a15c8d88434f8fa2496b7ef1ae560d-20211230 X-UUID: a8a15c8d88434f8fa2496b7ef1ae560d-20211230 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1140444455; Thu, 30 Dec 2021 17:36:22 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Dec 2021 17:36:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Dec 2021 17:36:21 +0800 From: Miles Chen To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , Nathan Chancellor , Nick Desaulniers , Jie Qiu , Junzhi Zhao CC: Miles Chen , Zhiqiang Lin , CK Hu , , , , , Subject: [PATCH v3] drm/mediatek: Fix unused-but-set variable warning Date: Thu, 30 Dec 2021 17:36:05 +0800 Message-ID: <20211230093610.28012-1-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org clang reports a unused-but-set variable warning: drivers/gpu/drm/mediatek/mtk_cec.c:85:6: warning: variable 'tmp' set but not used [-Wunused-but-set-variable] In current implementation, mtk_cec_mask() writes val into target register and ignores the mask. After talking to our hdmi experts, mtk_cec_mask() should read a register, clean only mask bits, and update (val | mask) bits to the register. Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support") Cc: Zhiqiang Lin Cc: CK Hu Cc: Matthias Brugger Signed-off-by: Miles Chen --- Change since v1: add Fixes tag Change since v2: add explanation of mtk_cec_mask() Change-Id: Iec6402b0532942f4d0e8bc56817eb87b95c03fad --- drivers/gpu/drm/mediatek/mtk_cec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c index e9cef5c0c8f7..cdfa648910b2 100644 --- a/drivers/gpu/drm/mediatek/mtk_cec.c +++ b/drivers/gpu/drm/mediatek/mtk_cec.c @@ -85,7 +85,7 @@ static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset, u32 tmp = readl(cec->regs + offset) & ~mask; tmp |= val & mask; - writel(val, cec->regs + offset); + writel(tmp, cec->regs + offset); } void mtk_cec_set_hpd_event(struct device *dev, -- 2.18.0