From:   Sam Protsenko <semen.protsenko@linaro.org>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
        Rob Herring <robh+dt@kernel.org>
Cc:     Chanho Park <chanho61.park@samsung.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] arm64: dts: exynos: Add missing gpm6 and gpm7 nodes to Exynos850
Date:   Mon,  3 Jan 2022 20:18:26 +0200
Message-Id: <20220103181826.2136-1-semen.protsenko@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

gpm6 and gpm7 nodes are missing in Exynos850 device tree. Next errors
are reported because of that:

    Missing node for bank gpm6 - invalid DTB
    Missing node for bank gpm7 - invalid DTB

Add missing nodes to make those available to use, and to fix boot
errors.

Fixes: e3493220fd3e ("arm64: dts: exynos: Add initial Exynos850 SoC support")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
NOTES:
  - Recommend to apply this patch after "arm64: dts: exynos: align
    pinctrl with dtschema in Exynos850"
  - This patch also brings back two interrupts removed in "arm64:
    dts: exynos: drop incorrectly placed wakeup interrupts in Exynos850"

 .../boot/dts/exynos/exynos850-pinctrl.dtsi    | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
index a71acf358d2d..f43e4a206282 100644
--- a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
@@ -194,6 +194,26 @@ gpm5: gpm5-gpio-bank {
 		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	gpm6: gpm6-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm7: gpm7-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	/* USI_CMGP0: HSI2C function */
 	hsi2c3_pins: hsi2c3-pins {
 		samsung,pins = "gpm0-0", "gpm1-0";
-- 
2.30.2