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References: <20211210210229.2991238-1-eranian@google.com> <20211210210229.2991238-4-eranian@google.com>
 <9c8d02ff-74a6-b8ba-c19b-9ee20da9af12@gmail.com>
In-Reply-To: <9c8d02ff-74a6-b8ba-c19b-9ee20da9af12@gmail.com>
From:   Stephane Eranian <eranian@google.com>
Date:   Mon, 3 Jan 2022 15:24:13 -0800
Message-ID: <CABPqkBTHYBujEzPDBwGub3oD5arNpGdZKwJqyLzFFwkhgpqgzQ@mail.gmail.com>
Subject: Re: [PATCH v4 03/14] perf/x86/amd: add AMD Fam19h Branch Sampling support
To:     Like Xu <like.xu.linux@gmail.com>
Cc:     linux-kernel@vger.kernel.org, peterz@infradead.org,
        kim.phillips@amd.com, acme@redhat.com, jolsa@redhat.com,
        songliubraving@fb.com, mpe@ellerman.id.au, maddy@linux.ibm.com
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On Wed, Dec 29, 2021 at 1:54 AM Like Xu <like.xu.linux@gmail.com> wrote:
>
> Hi Stephane,
>
> On 11/12/2021 5:02 am, Stephane Eranian wrote:
> > + * The BRS counter could be any counter, but there is no constraint on Fam19h,
> > + * therefore all counters are equal and thus we pick the first one: PMC0
>
> Are you assuming that no other counters can be enabled (guaranteed by the
> patched perf context) when BRS is enabled ? Otherwise the hard-coding of
> PMC0 may destroy scheduling freedom. Can we relax this condition?
>
You can use the other counters for any events. The BRS hardware is
programmed to watch PMC0. If
you activate BRS the event in PMC0 is the one triggering BRS capture.
When you do:
$ perf record -b -e cpu/branch-brs/,cycles ....

Given how perf record operates, it will force branch sampling on the two events.
And because branch sampling is coupled with PMC0, you will get multiplexing.
If you wanted to say use branch sampling on branch-brs, but not on
cycles, you would
not be able to do it with perf record, though the syscall interface supports it.

On AMD,  there are no event constraints, so forcing events using BRS
on PMC0 does not prevent
other events from being scheduled.

Hope this helps.