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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id q21sm467662pfu.176.2022.01.05.19.21.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jan 2022 19:21:26 -0800 (PST) Date: Wed, 05 Jan 2022 19:21:26 -0800 (PST) X-Google-Original-Date: Wed, 05 Jan 2022 19:20:58 PST (-0800) Subject: Re: [PATCH 09/12] riscv: extable: add `type` and `data` fields In-Reply-To: <20211118152155.GB9977@lakrids.cambridge.arm.com> CC: jszhang3@mail.ustc.edu.cn, tglx@linutronix.de, Paul Walmsley , aou@eecs.berkeley.edu, bjorn@kernel.org, ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, john.fastabend@gmail.com, kpsingh@kernel.org, masahiroy@kernel.org, michal.lkml@markovi.net, ndesaulniers@google.com, wangkefeng.wang@huawei.com, tongtiangen@huawei.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org, linux-kbuild@vger.kernel.org From: Palmer Dabbelt To: mark.rutland@arm.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 18 Nov 2021 07:21:55 PST (-0800), mark.rutland@arm.com wrote: > On Thu, Nov 18, 2021 at 07:42:49PM +0800, Jisheng Zhang wrote: >> On Thu, 18 Nov 2021 19:26:05 +0800 Jisheng Zhang wrote: >> >> > From: Jisheng Zhang >> > >> > This is a riscv port of commit d6e2cc564775("arm64: extable: add `type` >> > and `data` fields"). >> > >> > We will add specialized handlers for fixups, the `type` field is for >> > fixup handler type, the `data` field is used to pass specific data to >> > each handler, for example register numbers. >> > >> > Signed-off-by: Jisheng Zhang > >> > diff --git a/scripts/sorttable.c b/scripts/sorttable.c >> > index 0c031e47a419..5b5472b543f5 100644 >> > --- a/scripts/sorttable.c >> > +++ b/scripts/sorttable.c >> > @@ -376,9 +376,11 @@ static int do_file(char const *const fname, void *addr) >> > case EM_PARISC: >> > case EM_PPC: >> > case EM_PPC64: >> > - case EM_RISCV: >> > custom_sort = sort_relative_table; >> > break; >> > + case EM_RISCV: >> > + custom_sort = arm64_sort_relative_table; >> >> Hi Mark, Thomas, >> >> x86 and arm64 version of sort_relative_table routine are the same, I want to >> unify them, and then use the common function for riscv, but I'm not sure >> which name is better. Could you please suggest? > > I sent a patch last week which unifies them as > sort_relative_table_with_data(): > > https://lore.kernel.org/linux-arm-kernel/20211108114220.32796-1-mark.rutland@arm.com/ > > Thomas, are you happy with that patch? > > With your ack it could go via the riscv tree for v5.17 as a preparatory > cleanup in this series. > > Maybe we could get it in as a cleanup for v5.16-rc{2,3} ? I don't see anything on that thread, and looks like last time I had to touch sorttable I just took it via the RISC-V tree. I went ahead and put Mark's patch, along with this patch set, on my for-next. I had to fix up a few minor issues, so LMK if anything went off the rails. Thanks!