From:   Hongxing Zhu <hongxing.zhu@nxp.com>
To:     Jisheng Zhang <jszhang@kernel.org>,
        Jingoo Han <jingoohan1@gmail.com>,
        Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Rob Herring <robh@kernel.org>,
        =?iso-8859-2?Q?Krzysztof_Wilczy=F1ski?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>
CC:     "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: DEMO VERSION! [PATCH] PCI: dwc: Fix integrated MSI Receiver mask
 reg setting during resume
Thread-Topic: DEMO VERSION! [PATCH] PCI: dwc: Fix integrated MSI Receiver mask
 reg setting during resume
Thread-Index: AdgCzS9+v83JFPuhSyeUERkkeO1ynwAAD08g
Date:   Thu, 6 Jan 2022 07:23:02 +0000
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> -----Original Message-----
> From: Jisheng Zhang <jszhang@kernel.org>
> Sent: Sunday, December 26, 2021 3:40 PM
> To: Jingoo Han <jingoohan1@gmail.com>; Gustavo Pimentel
> <gustavo.pimentel@synopsys.com>; Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com>; Rob Herring <robh@kernel.org>; Krzysztof
> Wilczy=F1ski <kw@linux.com>; Bjorn Helgaas <bhelgaas@google.com>
> Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH] PCI: dwc: Fix integrated MSI Receiver
> mask reg setting during resume
>=20
> If the host which makes use of the IP's integrated MSI Receiver losts
> power during suspend, we call dw_pcie_setup_rc() to reinit the RC. But
> dw_pcie_setup_rc() always set the pp->irq_mask[ctrl] as ~0, so the mask
> register is always set as 0xffffffff incorrectly, thus the MSI can't work=
 after
> resume.
>=20
> Fix this issue by moving pp->irq_mask[ctrl] initialization to
> dw_pcie_host_init(), so we can correctly set the mask reg during both
> boot and resume.
>=20
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
[Richard Zhu] Hi Jisheng:
Based on i.MX8MQ and Marvell WIFI module, the MSI works fine after resume.
Thanks for your patch.
Tested-by: Richard Zhu <hongxing.zhu@nxp.com>

Best Regards
Richard Zhu

> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>=20
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
> b/drivers/pci/controller/dwc/pcie-designware-host.c
> index f4755f3a03be..2fa86f32d964 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -362,6 +362,12 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  			if (ret < 0)
>  				return ret;
>  		} else if (pp->has_msi_ctrl) {
> +			u32 ctrl, num_ctrls;
> +
> +			num_ctrls =3D pp->num_vectors /
> MAX_MSI_IRQS_PER_CTRL;
> +			for (ctrl =3D 0; ctrl < num_ctrls; ctrl++)
> +				pp->irq_mask[ctrl] =3D ~0;
> +
>  			if (!pp->msi_irq) {
>  				pp->msi_irq =3D
> platform_get_irq_byname_optional(pdev, "msi");
>  				if (pp->msi_irq < 0) {
> @@ -541,7 +547,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>=20
>  		/* Initialize IRQ Status array */
>  		for (ctrl =3D 0; ctrl < num_ctrls; ctrl++) {
> -			pp->irq_mask[ctrl] =3D ~0;
>  			dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
>  					    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
>  					    pp->irq_mask[ctrl]);
> --
> 2.34.1