Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49F0FC433FE for ; Thu, 6 Jan 2022 11:22:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238401AbiAFLWV (ORCPT ); Thu, 6 Jan 2022 06:22:21 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:52049 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238363AbiAFLWS (ORCPT ); Thu, 6 Jan 2022 06:22:18 -0500 Received: from droid04.amlogic.com (10.18.11.246) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2176.14; Thu, 6 Jan 2022 19:22:15 +0800 From: Xianwei Zhao To: , , , CC: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Xianwei Zhao Subject: [PATCH V4] arm64: dts: add support for S4 based Amlogic AQ222 Date: Thu, 6 Jan 2022 19:22:14 +0800 Message-ID: <20220106112214.6987-1-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.18.11.246] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add basic support for the Amlogic S4 based Amlogic AQ222 board: which describe components as follows: CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Xianwei Zhao --- V3 -> V4: cleaned up coding style. V2 -> V3: add of dts board compatible family. V1 -> V2: cleaned up coding style, modify CPU affinity of timer interrups, and modify GIC reg defintions. --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/meson-s4-s805x2-aq222.dts | 30 ++++++ arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 99 +++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-s4.dtsi diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 5148cd9e5146..faea74a45994 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -57,3 +57,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts new file mode 100644 index 000000000000..a942d7e06d6e --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "meson-s4.dtsi" + +/ { + model = "Amlogic Meson S4 AQ222 Development Board"; + compatible = "amlogic,aq222", "amlogic,s4"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_B; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + +}; + +&uart_B { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi new file mode 100644 index 000000000000..bf9ae1e1016b --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#include +#include + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; + interrupts = ; + }; + + apb4: apb4@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_B: serial@7a000 { + compatible = "amlogic,meson-s4-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x7a000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + }; + }; +}; base-commit: c5468e3c930d4d2937d3a842a85df0f74e95e152 -- 2.30.2