Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A25A2C4332F for ; Mon, 10 Jan 2022 12:58:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232579AbiAJM6f (ORCPT ); Mon, 10 Jan 2022 07:58:35 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:28342 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343562AbiAJM4L (ORCPT ); Mon, 10 Jan 2022 07:56:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1641819371; x=1673355371; h=from:to:cc:subject:date:message-id; bh=3Bk1/0hmaEKsEsqhTNPZn9424JbvOsw1HmScJhy+Q5Y=; b=L8YNHbyH5s6xsZ0Xp3N6iimlpT4pTLPMXPbBrFtwoJeNXU4NaiTvTdSs lKHhG9a+JKb+7Mklx/wcNy+4LXz16nzDhaXkMV1sZlNR7aLJ52fc3kkKm cLa2AxU9Vdwd1lz0PeK3vBiDxJd5tofoMtJNxWvMV69hpGYjj7J2F5++r E=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 10 Jan 2022 04:56:11 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Jan 2022 04:56:09 -0800 X-QCInternal: smtphost Received: from rajeevny-linux.qualcomm.com ([10.204.66.121]) by ironmsg02-blr.qualcomm.com with ESMTP; 10 Jan 2022 18:25:45 +0530 Received: by rajeevny-linux.qualcomm.com (Postfix, from userid 2363605) id EE593219EE; Mon, 10 Jan 2022 18:25:43 +0530 (IST) From: Rajeev Nandan To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Rajeev Nandan , linux-kernel@vger.kernel.org, sean@poorly.run, robdclark@gmail.com, robh+dt@kernel.org, robh@kernel.org, quic_abhinavk@quicinc.com, quic_kalyant@quicinc.com, quic_mkrishn@quicinc.com, jonathan@marek.ca, dmitry.baryshkov@linaro.org, airlied@linux.ie, daniel@ffwll.ch, swboyd@chromium.org Subject: [v2 0/3] drm/msm/dsi: Add 10nm dsi phy tuning configuration support Date: Mon, 10 Jan 2022 18:25:34 +0530 Message-Id: <1641819337-17037-1-git-send-email-quic_rajeevny@quicinc.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series is to add DSI PHY tuning support in Qualcomm Snapdragon SoCs with 10nm DSI PHY e.g. SC7180 In most cases the default values of DSI PHY tuning registers should be sufficient as they are fully optimized. However, in some cases (for example, where extreme board parasitics cause the eye shape to degrade), the override bits can be used to improve the signal quality. Different DSI PHY versions have different configurations to adjust the drive strength, drive level, de-emphasis, etc. The current series has only those configuration options supported by 10nm PHY, e.g. drive strength and drive level. The number of registers to configure the drive strength are different for 7nm PHY. The design can be extended to other DSI PHY versions if required, as each PHY version can have its callback to get the input from DT and prepare register values. Changes in v2: - Addressed dt-bindings comments (Stephen Boyd, Dmitry Baryshkov) - Split into generic code and 10nm-specific part (Dmitry Baryshkov) - Fix the backward compatibility (Dmitry Baryshkov) Rajeev Nandan (3): dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties drm/msm/dsi: Add dsi phy tuning configuration support drm/msm/dsi: Add 10nm dsi phy tuning configuration support .../bindings/display/msm/dsi-phy-10nm.yaml | 33 ++++++++++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 3 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 16 +++++++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 51 +++++++++++++++++++--- 4 files changed, 97 insertions(+), 6 deletions(-) -- 2.7.4