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References: <20211225193957.2195012-1-nikita.yoush@cogentembedded.com> <e0a56147-e800-914b-1df3-51ca7003a69d@gmail.com>
In-Reply-To: <e0a56147-e800-914b-1df3-51ca7003a69d@gmail.com>
From:   Geert Uytterhoeven <geert@linux-m68k.org>
Date:   Mon, 10 Jan 2022 16:06:30 +0100
Message-ID: <CAMuHMdW-S_SPgQmY6kxweNy4sYYKBorxnytk9c8101q7K2KB-w@mail.gmail.com>
Subject: Re: [PATCH] clk: renesas: r8a7799[05]: Add MLP clocks
To:     Sergei Shtylyov <sergei.shtylyov@gmail.com>
Cc:     Nikita Yushchenko <nikita.yoush@cogentembedded.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        linux-clk <linux-clk@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Sun, Dec 26, 2021 at 6:46 PM Sergei Shtylyov
<sergei.shtylyov@gmail.com> wrote:
> On 25.12.2021 22:39, Nikita Yushchenko wrote:
> > Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.
> >
> > Similar to other R-Car Gen3 SoC, exact information on parent for MLP
> > clock on E3 and D3 is not available. However, since parent for this
> > clocl is not anyhow software-controllable, the only harm from this
>
>     s/clocl/clock/. :-)
>
> > is inexact information exported via debugfs. So just keep the parent
> > set in the same way as with other Gen3 SoCs.
> >
> > Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.18, with the typos fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds