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References: <20211223093223.4725-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
In-Reply-To: <20211223093223.4725-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
From:   Geert Uytterhoeven <geert@linux-m68k.org>
Date:   Mon, 10 Jan 2022 16:20:54 +0100
Message-ID: <CAMuHMdXCcgG3ArRjiSAhKNdCbFV3ip7aAboWPKsZt2aeG6z7MA@mail.gmail.com>
Subject: Re: [PATCH] clk: renesas: r9a07g044: Update multiplier and divider
 values for PLL2/3
To:     Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        linux-clk <linux-clk@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Prabhakar <prabhakar.csengg@gmail.com>
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On Thu, Dec 23, 2021 at 10:32 AM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be 1600MHz,
> but with current multiplier and divider values this resulted to 1596MHz.
>
> This patch updates the multiplier and divider values for PLL2 and PLL3
> so that we get the exact (1600MHz) values.
>
> Fixes: 17f0ff3d49ff1 ("clk: renesas: Add support for R9A07G044 SoC")
> Suggested-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.18.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds